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Fri, 09 Jun 2023 12:56:42 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 359CufQA010963 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 9 Jun 2023 12:56:41 GMT Received: from hu-ppareek-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 9 Jun 2023 05:56:35 -0700 Date: Fri, 9 Jun 2023 18:26:31 +0530 From: Parikshit Pareek To: Konrad Dybcio CC: Will Deacon , Robin Murphy , "Joerg Roedel" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Andy Gross , Bjorn Andersson , Manivannan Sadhasivam , "Dmitry Baryshkov" , Marijn Suijten , Adam Skladowski , , , , , "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain Subject: Re: [PATCH 0/3] arm64: dts: qcom: sa8775p: Add interconnect to SMMU Message-ID: <20230609125631.GA29252@hu-ppareek-blr.qualcomm.com> References: <20230609054141.18938-1-quic_ppareek@quicinc.com> <79206b05-674b-1f6c-6eb1-ed45e6bd5637@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <79206b05-674b-1f6c-6eb1-ed45e6bd5637@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZhsxboR9byCRtdwLQRqycz4m3RQZPuhl X-Proofpoint-ORIG-GUID: ZhsxboR9byCRtdwLQRqycz4m3RQZPuhl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230609_055658_511584_94F007AA X-CRM114-Status: GOOD ( 18.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 09, 2023 at 10:52:26AM +0200, Konrad Dybcio wrote: > > > On 9.06.2023 07:41, Parikshit Pareek wrote: > > Some qcom SoCs have SMMUs, which need the interconnect bandwidth to be > > This series introduce the due support for associated interconnect, and > > setting of the due interconnect-bandwidth. Setting due interconnect > > bandwidth is needed to avoid the issues like [1], caused by not having > > due clock votes(indirectly dependent upon interconnect bandwidth). > > [1] ??? My bad. Intended to mention following: https://lore.kernel.org/linux-arm-msm/20230418165224.vmok75fwcjqdxspe@echanude/ Regards, Parikshit Pareek > > Konrad > > > > Parikshit Pareek (3): > > dt-bindings: arm-smmu: Add interconnect for qcom SMMUs > > arm64: dts: qcom: sa8775p: Add interconnect to PCIe SMMU > > iommu/arm-smmu-qcom: Add support for the interconnect > > > > .../devicetree/bindings/iommu/arm,smmu.yaml | 22 +++++++++++++++++++ > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 16 ++++++++++++++ > > 3 files changed, 42 insertions(+) > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel