* [PATCH AUTOSEL 6.3 02/17] arm64: dts: rockchip: add missing cache properties
2023-06-29 19:00 [PATCH AUTOSEL 6.3 01/17] arm64: dts: rockchip: fix USB regulator on ROCK64 Sasha Levin
@ 2023-06-29 19:00 ` Sasha Levin
2023-06-29 19:00 ` [PATCH AUTOSEL 6.3 07/17] arm64/hyperv: Use CPUHP_AP_HYPERV_ONLINE state to fix CPU online sequencing Sasha Levin
1 sibling, 0 replies; 4+ messages in thread
From: Sasha Levin @ 2023-06-29 19:00 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Krzysztof Kozlowski, Heiko Stuebner, Sasha Levin, robh+dt,
krzysztof.kozlowski+dt, conor+dt, pierre.gondois, clabbe,
cristian.ciocaltea, sebastian.reichel, zhangqing, kever.yang,
shreeya.patel, devicetree, linux-arm-kernel, linux-rockchip
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[ Upstream commit 42dcd054a6493e1adf292c3e246d1a2a9258942e ]
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'cache-size'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230421223149.115185-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
3 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index dd228a256a32a..2ae4bb7d5e62a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -97,6 +97,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 6d7a7bf72ac7e..e729e7a22b23a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -103,6 +103,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index f4eae4dde1751..ff4470a28ffa4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -223,6 +223,7 @@ l2_cache_l0: l2-cache-l0 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -232,6 +233,7 @@ l2_cache_l1: l2-cache-l1 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -241,6 +243,7 @@ l2_cache_l2: l2-cache-l2 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -250,6 +253,7 @@ l2_cache_l3: l2-cache-l3 {
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -259,6 +263,7 @@ l2_cache_b0: l2-cache-b0 {
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -268,6 +273,7 @@ l2_cache_b1: l2-cache-b1 {
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -277,6 +283,7 @@ l2_cache_b2: l2-cache-b2 {
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -286,6 +293,7 @@ l2_cache_b3: l2-cache-b3 {
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
+ cache-unified;
next-level-cache = <&l3_cache>;
};
@@ -295,6 +303,7 @@ l3_cache: l3-cache {
cache-line-size = <64>;
cache-sets = <4096>;
cache-level = <3>;
+ cache-unified;
};
};
--
2.39.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH AUTOSEL 6.3 07/17] arm64/hyperv: Use CPUHP_AP_HYPERV_ONLINE state to fix CPU online sequencing
2023-06-29 19:00 [PATCH AUTOSEL 6.3 01/17] arm64: dts: rockchip: fix USB regulator on ROCK64 Sasha Levin
2023-06-29 19:00 ` [PATCH AUTOSEL 6.3 02/17] arm64: dts: rockchip: add missing cache properties Sasha Levin
@ 2023-06-29 19:00 ` Sasha Levin
2023-06-29 22:18 ` Michael Kelley (LINUX)
1 sibling, 1 reply; 4+ messages in thread
From: Sasha Levin @ 2023-06-29 19:00 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Michael Kelley, Dexuan Cui, Wei Liu, Sasha Levin, kys, haiyangz,
catalin.marinas, will, linux-hyperv, linux-arm-kernel
From: Michael Kelley <mikelley@microsoft.com>
[ Upstream commit 52ae076c3a9b366b6fa9f7c7e67aed8b28716ed9 ]
State CPUHP_AP_HYPERV_ONLINE has been introduced to correctly sequence the
initialization of hyperv_pcpu_input_arg. Use this new state for Hyper-V
initialization so that hyperv_pcpu_input_arg is allocated early enough.
Signed-off-by: Michael Kelley <mikelley@microsoft.com>
Reviewed-by: Dexuan Cui <decui@microsoft.com>
Link: https://lore.kernel.org/r/1684862062-51576-2-git-send-email-mikelley@microsoft.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/hyperv/mshyperv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/hyperv/mshyperv.c b/arch/arm64/hyperv/mshyperv.c
index a406454578f07..f1b8a04ee9f26 100644
--- a/arch/arm64/hyperv/mshyperv.c
+++ b/arch/arm64/hyperv/mshyperv.c
@@ -67,7 +67,7 @@ static int __init hyperv_init(void)
if (ret)
return ret;
- ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/hyperv_init:online",
+ ret = cpuhp_setup_state(CPUHP_AP_HYPERV_ONLINE, "arm64/hyperv_init:online",
hv_common_cpu_init, hv_common_cpu_die);
if (ret < 0) {
hv_common_free();
--
2.39.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread