From: Alexandre Ghiti <alexghiti@rivosinc.com>
To: Jonathan Corbet <corbet@lwn.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Rob Herring <robh@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: [PATCH v4 03/10] riscv: Make legacy counter enum match the HW numbering
Date: Mon, 3 Jul 2023 14:46:40 +0200 [thread overview]
Message-ID: <20230703124647.215952-4-alexghiti@rivosinc.com> (raw)
In-Reply-To: <20230703124647.215952-1-alexghiti@rivosinc.com>
RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this
hardware counter from CSR_CYCLE is actually 2: make this offset match the
real hw offset so that we can directly expose those values to userspace.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
drivers/perf/riscv_pmu_legacy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c
index ca9e20bfc7ac..6a000abc28bb 100644
--- a/drivers/perf/riscv_pmu_legacy.c
+++ b/drivers/perf/riscv_pmu_legacy.c
@@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#define RISCV_PMU_LEGACY_CYCLE 0
-#define RISCV_PMU_LEGACY_INSTRET 1
+#define RISCV_PMU_LEGACY_INSTRET 2
static bool pmu_init_done;
--
2.39.2
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next prev parent reply other threads:[~2023-07-03 12:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 12:46 [PATCH v4 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-07-03 12:46 ` [PATCH v4 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-07-03 12:46 ` [PATCH v4 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-07-03 12:46 ` Alexandre Ghiti [this message]
2023-07-14 8:01 ` [PATCH v4 03/10] riscv: Make legacy counter enum match the HW numbering Atish Patra
2023-07-03 12:46 ` [PATCH v4 04/10] drivers: perf: Rename riscv pmu sbi driver Alexandre Ghiti
2023-07-14 8:01 ` Atish Patra
2023-07-03 12:46 ` [PATCH v4 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-07-14 8:03 ` Atish Patra
2023-07-03 12:46 ` [PATCH v4 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-07-14 8:03 ` Atish Patra
2023-07-03 12:46 ` [PATCH v4 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-07-14 8:46 ` Atish Patra
2023-07-20 8:36 ` Alexandre Ghiti
2023-07-03 12:46 ` [PATCH v4 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-07-03 13:03 ` Andrew Jones
2023-07-04 12:28 ` Vince Weaver
2023-07-14 8:50 ` Atish Patra
2023-07-03 12:46 ` [PATCH v4 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-07-14 9:29 ` Atish Patra
2023-07-03 12:46 ` [PATCH v4 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti
2023-07-14 9:29 ` Atish Patra
2023-07-14 9:07 ` [PATCH v4 00/10] riscv: Allow userspace to directly access perf counters Atish Patra
-- strict thread matches above, loose matches on Subject: below --
2023-07-27 14:14 Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
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