From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D141C001B0 for ; Thu, 13 Jul 2023 18:59:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0XA8+E5rh7kXfeHGT9A8HYBhWK58rr8DhDQhL6p6fHw=; b=lrozW8M6dLsXEl cD7nOvYV2ISULgyK+McS5AjYmSNQkrEzzfAuabLEYjXZrSypfCMg6cPuLVX/Pm2eQROaxo9PRJlNJ gTwNURX5uAxAXgM/46WydavSJ0qKsi+9uvwVGzfNPzMj3CorK4+waHmiF1NhfrMqx/o7inc6Zeb+x VQPpbaarLxswRckdwrgxmauhBf2c68Hd2565oRDtyWTDi9O8TFDXOPxdOTEQ3/WYYa3Kv6FwTgG3X OaQvLO5T6Fb+KPntvNkBnAu73t4R4Wf6ytGNSgUqJnvBk5RpWGAZf11naKPaOtm98H7RyXjpMr46s NGrX6KI1NWBR/tNh7YIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qK1WY-004BoS-2Y; Thu, 13 Jul 2023 18:58:46 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qK1WU-004Bo0-2t for linux-arm-kernel@lists.infradead.org; Thu, 13 Jul 2023 18:58:45 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36DIwZ9f098821; Thu, 13 Jul 2023 13:58:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1689274715; bh=6vvV5dSGBunU8apHatsM0+KaLcetuHWj5Zl/cBwlNKo=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=HuzzHD+pKEajI/6tgnfW/cPbY4wb5WswlTKMETgS/7Shca2EDQsSQuUAyD+USbdVo /7txeCLNYn0IIpcnXQ/+5NUrcmUsS+TgiqUwYx9G0+Ewte920G8oiWiPTQ3NL9BnDg eOANI9oNmDs/R7u8en1qScgwlayzao72BUMLUNfU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36DIwZfr001324 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Jul 2023 13:58:35 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 13 Jul 2023 13:58:35 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 13 Jul 2023 13:58:35 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36DIwZBS011984; Thu, 13 Jul 2023 13:58:35 -0500 Date: Thu, 13 Jul 2023 13:58:35 -0500 From: Nishanth Menon To: Andrew Davis CC: Jayesh Choudhary , , , , , , , , Subject: Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Message-ID: <20230713185835.ek5jskqyengvba56@ascertain> References: <20230710101705.154119-1-j-choudhary@ti.com> <20230710101705.154119-4-j-choudhary@ti.com> <20230712141828.lnpo4mhd5dv34rlz@census> <18310450-05f3-172c-e4bc-fda114f333a4@ti.com> <20230713182107.ashuygyg4x4j77s5@backboard> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230713_115843_069938_6F56EC38 X-CRM114-Status: GOOD ( 26.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 13:31-20230713, Andrew Davis wrote: > On 7/13/23 1:21 PM, Nishanth Menon wrote: > > On 21:01-20230713, Jayesh Choudhary wrote: > > > > > > > > > On 12/07/23 19:48, Nishanth Menon wrote: > > > > On 15:47-20230710, Jayesh Choudhary wrote: > > > > > From: Siddharth Vadapalli > > > > > > > > > > J784S4 SoC has 4 Serdes instances along with their respective WIZ > > > > > instances. Add device-tree nodes for them and disable them by default. > > > > > > > > > > Signed-off-by: Siddharth Vadapalli > > > > > [j-choudhary@ti.com: fix serdes_wiz clock order] > > > > > Signed-off-by: Jayesh Choudhary > > > > > --- > > > > NAK. This patch introduces the following dtbs_check warning. > > > > arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property > > > > > > > > > > Sorry for this. This property was added in the final board file. > > > I will fix it in the next revision. > > > I will add '0' as clock-property in the main file similar to j721e[1] > > > which will be overridden in the board file with required value to get > > > rid of this warning. > > > > That would follow what renesas (r8a774a1.dtsi) and imx > > (imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add > > documentation to the property to indicate expectation. Unless someone > > has objections to this approach. > > > > Would it work better to disable these nodes, only enabling them in the > board files when a real clock-frequency can be provided? > > My initial reaction would be to move the whole external reference clock > node to the board file since that is where it is provided, but seems > that would cause more churn in serdes_wiz* nodes than we would want.. I would prefer that as well, but I have'nt gone around looking for similar examples on other SoCs (Jayesh, can you check?). One other approach (alipine and few other places) has been for the bootloader to update the property set in dtb as 0, which is not needed in this case to the best of what I see.. just hoping we use a technique that most board folks are familiar with across SoCs. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel