* [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP
@ 2023-06-15 12:17 Teresa Remmet
2023-06-15 12:17 ` [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt Teresa Remmet
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
Hello,
this is an update for the phyCORE-i.MX8MP and phyBOARD-Pollux-i.MX8MP
including general cleanups, PMIC and SD-Card update.
Teresa
Christian Hemp (1):
arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt
Jonas Kuenstler (1):
arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks
assignment
Teresa Remmet (5):
arm64: dts: imx8mp-phycore-som: Order properties alphabetically
arm64: dts: imx8mp-phycore-som: Correct pad settings
arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes
arm64: dts: imx8mp-phycore-som: Add regulator names
arm64: dts: imx8mp-phycore-som: Update regulator output voltages
.../freescale/imx8mp-phyboard-pollux-rdk.dts | 2 +
.../dts/freescale/imx8mp-phycore-som.dtsi | 167 +++++++++---------
2 files changed, 82 insertions(+), 87 deletions(-)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically Teresa Remmet
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
From: Christian Hemp <c.hemp@phytec.de>
In some occasions the ethernet phy IRQ can not be detected correctly
by the SoC. This leads to a non detected link in Linux. The problem is
caused by the buffer that adjusts the voltage between ethernet phy
and SoC. To workaround this, remove the IRQ support for the ethernet
phy and use polling instead.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index ecc4bce6db97..e73f1711ec89 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -54,8 +54,6 @@ mdio {
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@@ -222,7 +220,6 @@ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
- MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
>;
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
2023-06-15 12:17 ` [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-07-18 1:14 ` Shawn Guo
2023-06-15 12:17 ` [PATCH 3/7] arm64: dts: imx8mp-phycore-som: Correct pad settings Teresa Remmet
` (4 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
Order properties alphabetically for easier comparability.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
.../dts/freescale/imx8mp-phycore-som.dtsi | 132 +++++++++---------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index e73f1711ec89..7970fa6f2a28 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -40,11 +40,11 @@ &A53_3 {
/* ethernet 1 */
&fec {
+ fsl,magic-packet;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- fsl,magic-packet;
status = "okay";
mdio {
@@ -53,13 +53,13 @@ mdio {
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
+ enet-phy-lane-no-swap;
reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
- enet-phy-lane-no-swap;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
};
@@ -73,8 +73,8 @@ som_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
};
};
@@ -83,97 +83,97 @@ &i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@25 {
- reg = <0x25>;
compatible = "nxp,pca9450c";
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio4>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0x25>;
regulators {
buck1: BUCK1 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
};
buck5: BUCK5 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
};
buck6: BUCK6 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
};
ldo1: LDO1 {
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1600000>;
};
ldo2: LDO2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1150000>;
+ regulator-min-microvolt = <800000>;
};
ldo3: LDO3 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
};
ldo4: LDO4 {
- regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
};
ldo5: LDO5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
};
};
eeprom@51 {
compatible = "atmel,24c32";
- reg = <0x51>;
pagesize = <32>;
+ reg = <0x51>;
};
rv3028: rtc@52 {
@@ -187,19 +187,19 @@ rv3028: rtc@52 {
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
status = "okay";
};
&wdog1 {
+ fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
status = "okay";
};
@@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
>;
};
@@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
>;
};
@@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
>;
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/7] arm64: dts: imx8mp-phycore-som: Correct pad settings
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
2023-06-15 12:17 ` [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt Teresa Remmet
2023-06-15 12:17 ` [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 4/7] arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes Teresa Remmet
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
Do not set reserved bits 0 and 3 in pad configuration.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
.../dts/freescale/imx8mp-phycore-som.dtsi | 26 +++++++++----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 7970fa6f2a28..8e06cb6f522b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -206,20 +206,20 @@ &wdog1 {
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
>;
};
@@ -236,21 +236,21 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140
>;
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/7] arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
` (2 preceding siblings ...)
2023-06-15 12:17 ` [PATCH 3/7] arm64: dts: imx8mp-phycore-som: Correct pad settings Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 5/7] arm64: dts: imx8mp-phycore-som: Add regulator names Teresa Remmet
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
We do not touch LDO2 and LDO4 in linux as they are bypassed.
So remove them completely from device tree.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
.../arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 8e06cb6f522b..ef86f2071d5b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -142,13 +142,6 @@ ldo1: LDO1 {
regulator-min-microvolt = <1600000>;
};
- ldo2: LDO2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1150000>;
- regulator-min-microvolt = <800000>;
- };
-
ldo3: LDO3 {
regulator-always-on;
regulator-boot-on;
@@ -156,11 +149,6 @@ ldo3: LDO3 {
regulator-min-microvolt = <800000>;
};
- ldo4: LDO4 {
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <800000>;
- };
-
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/7] arm64: dts: imx8mp-phycore-som: Add regulator names
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
` (3 preceding siblings ...)
2023-06-15 12:17 ` [PATCH 4/7] arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 6/7] arm64: dts: imx8mp-phycore-som: Update regulator output voltages Teresa Remmet
2023-06-15 12:17 ` [PATCH 7/7] arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment Teresa Remmet
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
Add regulator-names for more meaningful description.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index ef86f2071d5b..ad7a3e0b9089 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -101,6 +101,7 @@ buck1: BUCK1 {
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
+ regulator-name = "VDD_SOC (BUCK1)";
regulator-ramp-delay = <3125>;
};
@@ -111,6 +112,7 @@ buck2: BUCK2 {
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
+ regulator-name = "VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
};
@@ -119,6 +121,7 @@ buck4: BUCK4 {
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
+ regulator-name = "VDD_3V3 (BUCK4)";
};
buck5: BUCK5 {
@@ -126,6 +129,7 @@ buck5: BUCK5 {
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
+ regulator-name = "VDD_1V8 (BUCK5)";
};
buck6: BUCK6 {
@@ -133,6 +137,7 @@ buck6: BUCK6 {
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
+ regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
};
ldo1: LDO1 {
@@ -140,6 +145,7 @@ ldo1: LDO1 {
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
+ regulator-name = "NVCC_SNVS_1V8 (LDO1)";
};
ldo3: LDO3 {
@@ -147,6 +153,7 @@ ldo3: LDO3 {
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
+ regulator-name = "VDDA_1V8 (LDO3)";
};
ldo5: LDO5 {
@@ -154,6 +161,7 @@ ldo5: LDO5 {
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
+ regulator-name = "NVCC_SD2 (LDO5)";
};
};
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6/7] arm64: dts: imx8mp-phycore-som: Update regulator output voltages
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
` (4 preceding siblings ...)
2023-06-15 12:17 ` [PATCH 5/7] arm64: dts: imx8mp-phycore-som: Add regulator names Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 7/7] arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment Teresa Remmet
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
Set the regulator voltages to the min and max values the i.MX8MP
requires and not what the PMIC provides.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
.../dts/freescale/imx8mp-phycore-som.dtsi | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index ad7a3e0b9089..d3e7d3087ec1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -99,8 +99,8 @@ regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <2187500>;
- regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <805000>;
regulator-name = "VDD_SOC (BUCK1)";
regulator-ramp-delay = <3125>;
};
@@ -110,8 +110,8 @@ buck2: BUCK2 {
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <2187500>;
- regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <805000>;
regulator-name = "VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
};
@@ -119,40 +119,40 @@ buck2: BUCK2 {
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3 (BUCK4)";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8 (BUCK5)";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-min-microvolt = <1045000>;
regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <1710000>;
regulator-name = "NVCC_SNVS_1V8 (LDO1)";
};
ldo3: LDO3 {
regulator-always-on;
regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
regulator-name = "VDDA_1V8 (LDO3)";
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 7/7] arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
` (5 preceding siblings ...)
2023-06-15 12:17 ` [PATCH 6/7] arm64: dts: imx8mp-phycore-som: Update regulator output voltages Teresa Remmet
@ 2023-06-15 12:17 ` Teresa Remmet
6 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-06-15 12:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-arm-kernel, upstream
From: Jonas Kuenstler <j.kuenstler@phytec.de>
Add the missing usdhc2 root clock to 200MHz to be able to support
SDR104 mode for SD-Card on phyBOARD-Pollux-i.MX8MP.
Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 6aa720bafe28..0a51ddbc62df 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -103,6 +103,8 @@ &uart1 {
/* SD-Card */
&usdhc2 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically
2023-06-15 12:17 ` [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically Teresa Remmet
@ 2023-07-18 1:14 ` Shawn Guo
2023-07-18 13:43 ` Teresa Remmet
0 siblings, 1 reply; 10+ messages in thread
From: Shawn Guo @ 2023-07-18 1:14 UTC (permalink / raw)
To: Teresa Remmet
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
linux-arm-kernel, upstream
On Thu, Jun 15, 2023 at 02:17:30PM +0200, Teresa Remmet wrote:
> Order properties alphabetically for easier comparability.
>
> Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
> ---
> .../dts/freescale/imx8mp-phycore-som.dtsi | 132 +++++++++---------
> 1 file changed, 66 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index e73f1711ec89..7970fa6f2a28 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -40,11 +40,11 @@ &A53_3 {
>
> /* ethernet 1 */
> &fec {
> + fsl,magic-packet;
> + phy-handle = <ðphy1>;
> + phy-mode = "rgmii-id";
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec>;
> - phy-mode = "rgmii-id";
> - phy-handle = <ðphy1>;
> - fsl,magic-packet;
> status = "okay";
>
> mdio {
> @@ -53,13 +53,13 @@ mdio {
>
> ethphy1: ethernet-phy@0 {
> compatible = "ethernet-phy-ieee802.3-c22";
> + enet-phy-lane-no-swap;
> reg = <0>;
> - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> ti,min-output-impedance;
> - enet-phy-lane-no-swap;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> };
> };
> };
> @@ -73,8 +73,8 @@ som_flash: flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <80000000>;
> - spi-tx-bus-width = <1>;
> spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <1>;
> };
> };
>
> @@ -83,97 +83,97 @@ &i2c1 {
> pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pinctrl_i2c1>;
> pinctrl-1 = <&pinctrl_i2c1_gpio>;
> - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "okay";
>
> pmic: pmic@25 {
> - reg = <0x25>;
> compatible = "nxp,pca9450c";
> + interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&gpio4>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pmic>;
> - interrupt-parent = <&gpio4>;
> - interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> + reg = <0x25>;
We generally arrange properties in order of:
- compatible
- reg
- other generic properties
- device specific properties
- vendor specific properties
- status
Shawn
>
> regulators {
> buck1: BUCK1 {
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <2187500>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <2187500>;
> + regulator-min-microvolt = <600000>;
> regulator-ramp-delay = <3125>;
> };
>
> buck2: BUCK2 {
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <2187500>;
> - regulator-boot-on;
> - regulator-always-on;
> - regulator-ramp-delay = <3125>;
> nxp,dvs-run-voltage = <950000>;
> nxp,dvs-standby-voltage = <850000>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <2187500>;
> + regulator-min-microvolt = <600000>;
> + regulator-ramp-delay = <3125>;
> };
>
> buck4: BUCK4 {
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3400000>;
> + regulator-min-microvolt = <600000>;
> };
>
> buck5: BUCK5 {
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3400000>;
> + regulator-min-microvolt = <600000>;
> };
>
> buck6: BUCK6 {
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3400000>;
> + regulator-min-microvolt = <600000>;
> };
>
> ldo1: LDO1 {
> - regulator-min-microvolt = <1600000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <1600000>;
> };
>
> ldo2: LDO2 {
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1150000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1150000>;
> + regulator-min-microvolt = <800000>;
> };
>
> ldo3: LDO3 {
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <800000>;
> };
>
> ldo4: LDO4 {
> - regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <800000>;
> };
>
> ldo5: LDO5 {
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
> regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <1800000>;
> };
> };
> };
>
> eeprom@51 {
> compatible = "atmel,24c32";
> - reg = <0x51>;
> pagesize = <32>;
> + reg = <0x51>;
> };
>
> rv3028: rtc@52 {
> @@ -187,19 +187,19 @@ rv3028: rtc@52 {
> &usdhc3 {
> assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
> assigned-clock-rates = <400000000>;
> + bus-width = <8>;
> + non-removable;
> pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc3>;
> pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> - bus-width = <8>;
> - non-removable;
> status = "okay";
> };
>
> &wdog1 {
> + fsl,ext-reset-output;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_wdog>;
> - fsl,ext-reset-output;
> status = "okay";
> };
>
> @@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
> MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
> MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
> MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
> - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
> MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
> MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
> MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
> MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
> MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
> MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
> + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
> >;
> };
>
> @@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>
> pinctrl_i2c1: i2c1grp {
> fsl,pins = <
> - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
> MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
> + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
> >;
> };
>
> @@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
>
> pinctrl_usdhc3: usdhc3grp {
> fsl,pins = <
> - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
> - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
> MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
> MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
> MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
> MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
> MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
> - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
> - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
> - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
> - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
> >;
> };
>
> pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> fsl,pins = <
> - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
> - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
> MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
> MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
> MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
> MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
> MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
> - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
> - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
> - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
> - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
> >;
> };
>
> pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> fsl,pins = <
> - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
> - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
> MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
> MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
> MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
> MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
> MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
> - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
> - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
> - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
> - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
> >;
> };
>
> --
> 2.25.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically
2023-07-18 1:14 ` Shawn Guo
@ 2023-07-18 13:43 ` Teresa Remmet
0 siblings, 0 replies; 10+ messages in thread
From: Teresa Remmet @ 2023-07-18 13:43 UTC (permalink / raw)
To: shawnguo@kernel.org
Cc: kernel@pengutronix.de, linux-imx@nxp.com, s.hauer@pengutronix.de,
festevam@gmail.com, upstream@lists.phytec.de,
linux-arm-kernel@lists.infradead.org, conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org
Am Dienstag, dem 18.07.2023 um 09:14 +0800 schrieb Shawn Guo:
> > @@ -83,97 +83,97 @@ &i2c1 {
> > pinctrl-names = "default", "gpio";
> > pinctrl-0 = <&pinctrl_i2c1>;
> > pinctrl-1 = <&pinctrl_i2c1_gpio>;
> > - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH |
> > GPIO_OPEN_DRAIN)>;
> > scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH |
> > GPIO_OPEN_DRAIN)>;
> > + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH |
> > GPIO_OPEN_DRAIN)>;
> > status = "okay";
> >
> > pmic: pmic@25 {
> > - reg = <0x25>;
> > compatible = "nxp,pca9450c";
> > + interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-parent = <&gpio4>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_pmic>;
> > - interrupt-parent = <&gpio4>;
> > - interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> > + reg = <0x25>;
>
> We generally arrange properties in order of:
>
> - compatible
> - reg
> - other generic properties
> - device specific properties
> - vendor specific properties
> - status
>
> Shawn
Okay, thank you. I will go though the device tree and check the order
based on this.
Teresa
--
PHYTEC Messtechnik GmbH | Barcelona-Allee 1 | 55129 Mainz, Germany
Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber,
Dipl.-Ing. (FH) Markus Lickes | Handelsregister Mainz HRB 4656 |
Finanzamt Mainz | St.Nr. 266500608, DE 149059855
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-07-19 6:34 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-15 12:17 [PATCH 0/7] Update for phyBOARD-Pollux-i.MX8MP Teresa Remmet
2023-06-15 12:17 ` [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt Teresa Remmet
2023-06-15 12:17 ` [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Order properties alphabetically Teresa Remmet
2023-07-18 1:14 ` Shawn Guo
2023-07-18 13:43 ` Teresa Remmet
2023-06-15 12:17 ` [PATCH 3/7] arm64: dts: imx8mp-phycore-som: Correct pad settings Teresa Remmet
2023-06-15 12:17 ` [PATCH 4/7] arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes Teresa Remmet
2023-06-15 12:17 ` [PATCH 5/7] arm64: dts: imx8mp-phycore-som: Add regulator names Teresa Remmet
2023-06-15 12:17 ` [PATCH 6/7] arm64: dts: imx8mp-phycore-som: Update regulator output voltages Teresa Remmet
2023-06-15 12:17 ` [PATCH 7/7] arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment Teresa Remmet
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).