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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jun 15, 2023 at 02:17:30PM +0200, Teresa Remmet wrote: > Order properties alphabetically for easier comparability. > > Signed-off-by: Teresa Remmet > --- > .../dts/freescale/imx8mp-phycore-som.dtsi | 132 +++++++++--------- > 1 file changed, 66 insertions(+), 66 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > index e73f1711ec89..7970fa6f2a28 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi > @@ -40,11 +40,11 @@ &A53_3 { > > /* ethernet 1 */ > &fec { > + fsl,magic-packet; > + phy-handle = <ðphy1>; > + phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_fec>; > - phy-mode = "rgmii-id"; > - phy-handle = <ðphy1>; > - fsl,magic-packet; > status = "okay"; > > mdio { > @@ -53,13 +53,13 @@ mdio { > > ethphy1: ethernet-phy@0 { > compatible = "ethernet-phy-ieee802.3-c22"; > + enet-phy-lane-no-swap; > reg = <0>; > - ti,rx-internal-delay = ; > - ti,tx-internal-delay = ; > - ti,fifo-depth = ; > ti,clk-output-sel = ; > + ti,fifo-depth = ; > ti,min-output-impedance; > - enet-phy-lane-no-swap; > + ti,rx-internal-delay = ; > + ti,tx-internal-delay = ; > }; > }; > }; > @@ -73,8 +73,8 @@ som_flash: flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <80000000>; > - spi-tx-bus-width = <1>; > spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; > }; > }; > > @@ -83,97 +83,97 @@ &i2c1 { > pinctrl-names = "default", "gpio"; > pinctrl-0 = <&pinctrl_i2c1>; > pinctrl-1 = <&pinctrl_i2c1_gpio>; > - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > status = "okay"; > > pmic: pmic@25 { > - reg = <0x25>; > compatible = "nxp,pca9450c"; > + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; > + interrupt-parent = <&gpio4>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pmic>; > - interrupt-parent = <&gpio4>; > - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; > + reg = <0x25>; We generally arrange properties in order of: - compatible - reg - other generic properties - device specific properties - vendor specific properties - status Shawn > > regulators { > buck1: BUCK1 { > - regulator-min-microvolt = <600000>; > - regulator-max-microvolt = <2187500>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <2187500>; > + regulator-min-microvolt = <600000>; > regulator-ramp-delay = <3125>; > }; > > buck2: BUCK2 { > - regulator-min-microvolt = <600000>; > - regulator-max-microvolt = <2187500>; > - regulator-boot-on; > - regulator-always-on; > - regulator-ramp-delay = <3125>; > nxp,dvs-run-voltage = <950000>; > nxp,dvs-standby-voltage = <850000>; > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <2187500>; > + regulator-min-microvolt = <600000>; > + regulator-ramp-delay = <3125>; > }; > > buck4: BUCK4 { > - regulator-min-microvolt = <600000>; > - regulator-max-microvolt = <3400000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > }; > > buck5: BUCK5 { > - regulator-min-microvolt = <600000>; > - regulator-max-microvolt = <3400000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > }; > > buck6: BUCK6 { > - regulator-min-microvolt = <600000>; > - regulator-max-microvolt = <3400000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > }; > > ldo1: LDO1 { > - regulator-min-microvolt = <1600000>; > - regulator-max-microvolt = <3300000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1600000>; > }; > > ldo2: LDO2 { > - regulator-min-microvolt = <800000>; > - regulator-max-microvolt = <1150000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1150000>; > + regulator-min-microvolt = <800000>; > }; > > ldo3: LDO3 { > - regulator-min-microvolt = <800000>; > - regulator-max-microvolt = <3300000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <800000>; > }; > > ldo4: LDO4 { > - regulator-min-microvolt = <800000>; > regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <800000>; > }; > > ldo5: LDO5 { > - regulator-min-microvolt = <1800000>; > - regulator-max-microvolt = <3300000>; > - regulator-boot-on; > regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1800000>; > }; > }; > }; > > eeprom@51 { > compatible = "atmel,24c32"; > - reg = <0x51>; > pagesize = <32>; > + reg = <0x51>; > }; > > rv3028: rtc@52 { > @@ -187,19 +187,19 @@ rv3028: rtc@52 { > &usdhc3 { > assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; > assigned-clock-rates = <400000000>; > + bus-width = <8>; > + non-removable; > pinctrl-names = "default", "state_100mhz", "state_200mhz"; > pinctrl-0 = <&pinctrl_usdhc3>; > pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > - bus-width = <8>; > - non-removable; > status = "okay"; > }; > > &wdog1 { > + fsl,ext-reset-output; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_wdog>; > - fsl,ext-reset-output; > status = "okay"; > }; > > @@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 > MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 > MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 > MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 > - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 > MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 > MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 > MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 > MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 > MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 > MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 > + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 > >; > }; > > @@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 > > pinctrl_i2c1: i2c1grp { > fsl,pins = < > - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 > MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 > + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 > >; > }; > > @@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 > > pinctrl_usdhc3: usdhc3grp { > fsl,pins = < > - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 > - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 > MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 > MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 > MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 > MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 > MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 > - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 > - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 > - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 > - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 > >; > }; > > pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > fsl,pins = < > - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 > - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 > MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 > MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 > MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 > MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 > MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 > - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 > - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 > - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 > - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 > >; > }; > > pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > fsl,pins = < > - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 > MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 > MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 > MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 > MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 > MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 > - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 > - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 > - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 > - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 > >; > }; > > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel