From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBBD9EB64DC for ; Fri, 21 Jul 2023 05:27:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NSP6wq9IC5pugyLETbxPBek09ZDoC0H0NjM6HrWsqdA=; b=Qe57zbHn1SnGA8 CBl7S0QyiSp8feM/tr/2zP0p5FW1AoXIe/LDaGtLhBbI/UbOs12mTzWyaE1p4Bq0JZcfiMCwoB9H+ 5WAbBf8P1fKuC33neu16EyhpQa9BJOzbFIUyaMC7k7Z9LuOaPQNiBfyE2Qpyo9z6baEE9Qv1wUUAb 76ZgjC3S3WpaRwsLVNvoAqqNhy3XgVXTYQd4R+uJ97e39r1U0yKKhLp2uv3numvMJM71zbwGifdmn 5IPDr9bJdSp2cMqRvR4WNnCM2wR3tNWUIgKrTSxXrI5/d8NyviZIF16CiJFF3yQuzJ0bSivQo5I6G pTVv+R90TSDYUUQrs7QQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMifx-00CvBt-0i; Fri, 21 Jul 2023 05:27:37 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMifu-00CvB4-18 for linux-arm-kernel@lists.infradead.org; Fri, 21 Jul 2023 05:27:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9F10C61040; Fri, 21 Jul 2023 05:27:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D285C433C9; Fri, 21 Jul 2023 05:27:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1689917252; bh=1afuGQPjD3KQx3/4ehbMFfIxt3CD7zfKs3ykg3JJelE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lECO1F7bktgAsOfWmqS2j/yGnDirF99NzuIcsBZJOMFEISz0FNvFWz+j88jdaqk4o YgegmaKK9BCb0lgGHbKo7IB4GRDw2v5rhYVTwn31Cr9ruXOoPA1wmBA3psI0nXislB /f7OVGBoznS8wQy2v2jJlOlXV+58hBvjHRYViUuc= Date: Fri, 21 Jul 2023 07:27:29 +0200 From: Greg KH To: Easwar Hariharan Cc: stable@vger.kernel.org, easwar.hariharan@microsoft.com, catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net, robin.murphy@arm.com, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev Subject: Re: [PATCH 5.15 2/4] arm64: errata: Add workaround for TSB flush failures Message-ID: <2023072131-supremacy-modify-f9ff@gregkh> References: <1689895414-17425-1-git-send-email-eahariha@linux.microsoft.com> <1689895414-17425-3-git-send-email-eahariha@linux.microsoft.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1689895414-17425-3-git-send-email-eahariha@linux.microsoft.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230720_222734_496952_D709D5AA X-CRM114-Status: GOOD ( 21.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 20, 2023 at 04:23:32PM -0700, Easwar Hariharan wrote: > From: Suzuki K Poulose > > commit fa82d0b4b833790ac4572377fb777dcea24a9d69 upstream > > Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers > from errata, where a TSB (trace synchronization barrier) > fails to flush the trace data completely, when executed from > a trace prohibited region. In Linux we always execute it > after we have moved the PE to trace prohibited region. So, > we can apply the workaround every time a TSB is executed. > > The work around is to issue two TSB consecutively. > > NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying > that a late CPU could be blocked from booting if it is the > first CPU that requires the workaround. This is because we > do not allow setting a cpu_hwcaps after the SMP boot. The > other alternative is to use "this_cpu_has_cap()" instead > of the faster system wide check, which may be a bit of an > overhead, given we may have to do this in nvhe KVM host > before a guest entry. > > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Mark Rutland > Cc: Anshuman Khandual > Cc: Marc Zyngier > Acked-by: Catalin Marinas > Reviewed-by: Mathieu Poirier > Reviewed-by: Anshuman Khandual > Signed-off-by: Suzuki K Poulose > Link: https://lore.kernel.org/r/20211019163153.3692640-4-suzuki.poulose@arm.com > Signed-off-by: Will Deacon > --- > Documentation/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/Kconfig | 33 ++++++++++++++++++++++++++ > arch/arm64/include/asm/barrier.h | 16 ++++++++++++- > arch/arm64/kernel/cpu_errata.c | 19 +++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 5 files changed, 72 insertions(+), 1 deletion(-) As you forwarded this patch on to me, you forgot to sign-off on it :( I've taken patch 1/4 of this series, but not the rest. Please redo them, and send the needed backports for 6.1.y and 6.4.y as a separate series (obviously I can't apply patches in a series to trees that already have them.) thanks, greg k-h _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel