[PATCH v1 0/3] iio: adc: meson: tune init sequence

[PATCH v1 0/3] iio: adc: meson: tune init sequence

[George Stark]

This patch is a part of effort to support meson a1 SoC and make meson saradc driver
independent from vendor boot code initialization in common.

Information was taken from vendor kernel 5.4, 4.19 and vendor uboot 2019.
Most of the bits are undocumented at all or it's not said how they affect measuring.

All those bits are already initialized in bl* code and since kernel driver dosn't
rewrite or reset any registers but only changes some bits at init stage everything
works fine.

Test procedure is rather simple - one can change those bits in runtime
(e.g. using devmem) and try to read channels (cat /sys/bus/platform/drivers/meson-saradc/.../iio:device0/*)
changing some of those bits leads to measure procedure errors or abnormal results.
Another test is build meson saradc as module, reset adc by reset bit, reload module
and compare measure results to those got before reset.

George Stark (3):
  iio: adc: meson: init channels 0,1 input muxes
  iio: adc: meson: init internal continuous ring counter
  iio: adc: meson: init voltage control bits

 drivers/iio/adc/meson_saradc.c | 73 ++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

-- 
2.38.4


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[PATCH v1 0/3] iio: adc: meson: tune init sequence

[George Stark]

This patch is a part of effort to support meson a1 SoC and make meson saradc driver
independent from vendor boot code initialization in common.

Information was taken from vendor kernel 5.4, 4.19 and vendor uboot 2019.
Most of the bits are undocumented at all or it's not said how they affect measuring.

All those bits are already initialized in bl* code and since kernel driver dosn't
rewrite or reset any registers but only changes some bits at init stage everything
works fine.

Test procedure is rather simple - one can change those bits in runtime
(e.g. using devmem) and try to read channels (cat /sys/bus/platform/drivers/meson-saradc/.../iio:device0/*)
changing some of those bits leads to measure procedure errors or abnormal results.
Another test is build meson saradc as module, reset adc by reset bit, reload module
and compare measure results to those got before reset.

George Stark (3):
  iio: adc: meson: init channels 0,1 input muxes
  iio: adc: meson: init internal continuous ring counter
  iio: adc: meson: init voltage control bits

 drivers/iio/adc/meson_saradc.c | 73 ++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

-- 
2.38.4


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[PATCH v1 1/3] iio: adc: meson: init channels 0,1 input muxes

[George Stark]

Set up input channels 0,1 muxes in the same way as for the channels 2-7
later in the code.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 2411cc864ccd..524e5569381e 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -899,6 +899,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
 			   regval);
 
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
+
 	/*
 	 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
 	 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
-- 
2.38.4


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[PATCH v1 1/3] iio: adc: meson: init channels 0,1 input muxes

[George Stark]

Set up input channels 0,1 muxes in the same way as for the channels 2-7
later in the code.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 2411cc864ccd..524e5569381e 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -899,6 +899,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
 			   regval);
 
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
+
 	/*
 	 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
 	 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
-- 
2.38.4


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[PATCH v1 2/3] iio: adc: meson: init internal continuous ring counter

[George Stark]

Disable internal continuous ring counter at init stage. Disable value
depends on SoC family: gxl and later SoCs write 1, others write 0.
This bit are inited in vendor boot code (bl2, bl33) already so do it
in the driver to not depend on other code.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 524e5569381e..806ba7cd7320 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -313,6 +313,7 @@ struct meson_sar_adc_param {
 	u8					temperature_trimming_bits;
 	unsigned int				temperature_multiplier;
 	unsigned int				temperature_divider;
+	u8					disable_ring_counter;
 };
 
 struct meson_sar_adc_data {
@@ -967,6 +968,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 				   MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
 	}
 
+	regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
+			    priv->param->disable_ring_counter);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
+			   regval);
+
 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
@@ -1196,6 +1203,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
+	.disable_ring_counter = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1204,6 +1212,7 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
+	.disable_ring_counter = 1,
 };
 
 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
-- 
2.38.4


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[PATCH v1 2/3] iio: adc: meson: init internal continuous ring counter

[George Stark]

Disable internal continuous ring counter at init stage. Disable value
depends on SoC family: gxl and later SoCs write 1, others write 0.
This bit are inited in vendor boot code (bl2, bl33) already so do it
in the driver to not depend on other code.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 524e5569381e..806ba7cd7320 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -313,6 +313,7 @@ struct meson_sar_adc_param {
 	u8					temperature_trimming_bits;
 	unsigned int				temperature_multiplier;
 	unsigned int				temperature_divider;
+	u8					disable_ring_counter;
 };
 
 struct meson_sar_adc_data {
@@ -967,6 +968,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 				   MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
 	}
 
+	regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
+			    priv->param->disable_ring_counter);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
+			   regval);
+
 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
@@ -1196,6 +1203,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
+	.disable_ring_counter = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1204,6 +1212,7 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
+	.disable_ring_counter = 1,
 };
 
 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
-- 
2.38.4


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[PATCH v1 3/3] iio: adc: meson: init voltage control bits

[George Stark]

Define and init voltage configuration bits. Those bits are inited in
vendor boot code (bl2, bl33) already so do it in the driver to not depend
on other code.

Introduced bits:
REG11[0] - selects Vref. 0 - calibration voltage, 1 - VDDA. txlx and later
           SoCs support VDDA or calibration voltage as Vref, but others
           support only calibration voltage. For newer platforms vendor
	   uses VDDA as default.
REG11[1] - reserved bit. g12a and later SoCs must write 1, others SoCs
           write 0.
REG11[5] - Vref voltage. 0 - 0.9v, 1 - 1.8v. g12a and later SoCs must
           write 0, others SoCs write 1.
REG11[6] - selects common-mode voltage, 0: from AVDD, 1: from Vref.
           g12a and later SoCs must write 0, others SoCs write 1.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 48 ++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 806ba7cd7320..05fb30b81b8d 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -156,6 +156,10 @@
  */
 #define MESON_SAR_ADC_REG11					0x2c
 	#define MESON_SAR_ADC_REG11_BANDGAP_EN			BIT(13)
+	#define MESON_SAR_ADC_REG11_CMV_SEL                     BIT(6)
+	#define MESON_SAR_ADC_REG11_VREF_VOLTAGE                BIT(5)
+	#define MESON_SAR_ADC_REG11_EOC                         BIT(1)
+	#define MESON_SAR_ADC_REG11_VREF_SEL                    BIT(0)
 
 #define MESON_SAR_ADC_REG13					0x34
 	#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK	GENMASK(13, 8)
@@ -216,6 +220,11 @@
 	.datasheet_name = "SAR_ADC_MUX_"#_sel,				\
 }
 
+enum meson_sar_adc_vref_sel {
+	VREF_CALIBATION_VOLTAGE = 0,
+	VREF_VDDA = 1,
+};
+
 enum meson_sar_adc_avg_mode {
 	NO_AVERAGING = 0x0,
 	MEAN_AVERAGING = 0x1,
@@ -314,6 +323,12 @@ struct meson_sar_adc_param {
 	unsigned int				temperature_multiplier;
 	unsigned int				temperature_divider;
 	u8					disable_ring_counter;
+	bool					has_reg11;
+	bool					has_vref_select;
+	u8					vref_select;
+	u8					cmv_select;
+	u8					adc_eoc;
+	enum meson_sar_adc_vref_sel		vref_volatge;
 };
 
 struct meson_sar_adc_data {
@@ -974,6 +989,29 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 			   MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
 			   regval);
 
+	if (priv->param->has_reg11) {
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_EOC, regval);
+
+		if (priv->param->has_vref_select) {
+			regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,
+					    priv->param->vref_select);
+			regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+					   MESON_SAR_ADC_REG11_VREF_SEL, regval);
+		}
+
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
+				    priv->param->vref_volatge);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
+
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
+				    priv->param->cmv_select);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_CMV_SEL, regval);
+	}
+
 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
@@ -1195,6 +1233,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 10,
+	.has_reg11 = true,
+	.vref_volatge = 1,
+	.cmv_select = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
@@ -1204,6 +1245,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
 	.disable_ring_counter = 1,
+	.has_reg11 = true,
+	.vref_volatge = 1,
+	.cmv_select = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1213,6 +1257,10 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
 	.disable_ring_counter = 1,
+	.has_reg11 = true,
+	.adc_eoc = 1,
+	.has_vref_select = true,
+	.vref_select = VREF_VDDA,
 };
 
 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
-- 
2.38.4


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[PATCH v1 3/3] iio: adc: meson: init voltage control bits

[George Stark]

Define and init voltage configuration bits. Those bits are inited in
vendor boot code (bl2, bl33) already so do it in the driver to not depend
on other code.

Introduced bits:
REG11[0] - selects Vref. 0 - calibration voltage, 1 - VDDA. txlx and later
           SoCs support VDDA or calibration voltage as Vref, but others
           support only calibration voltage. For newer platforms vendor
	   uses VDDA as default.
REG11[1] - reserved bit. g12a and later SoCs must write 1, others SoCs
           write 0.
REG11[5] - Vref voltage. 0 - 0.9v, 1 - 1.8v. g12a and later SoCs must
           write 0, others SoCs write 1.
REG11[6] - selects common-mode voltage, 0: from AVDD, 1: from Vref.
           g12a and later SoCs must write 0, others SoCs write 1.

Signed-off-by: George Stark <gnstark@sberdevices.ru>
---
 drivers/iio/adc/meson_saradc.c | 48 ++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 806ba7cd7320..05fb30b81b8d 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -156,6 +156,10 @@
  */
 #define MESON_SAR_ADC_REG11					0x2c
 	#define MESON_SAR_ADC_REG11_BANDGAP_EN			BIT(13)
+	#define MESON_SAR_ADC_REG11_CMV_SEL                     BIT(6)
+	#define MESON_SAR_ADC_REG11_VREF_VOLTAGE                BIT(5)
+	#define MESON_SAR_ADC_REG11_EOC                         BIT(1)
+	#define MESON_SAR_ADC_REG11_VREF_SEL                    BIT(0)
 
 #define MESON_SAR_ADC_REG13					0x34
 	#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK	GENMASK(13, 8)
@@ -216,6 +220,11 @@
 	.datasheet_name = "SAR_ADC_MUX_"#_sel,				\
 }
 
+enum meson_sar_adc_vref_sel {
+	VREF_CALIBATION_VOLTAGE = 0,
+	VREF_VDDA = 1,
+};
+
 enum meson_sar_adc_avg_mode {
 	NO_AVERAGING = 0x0,
 	MEAN_AVERAGING = 0x1,
@@ -314,6 +323,12 @@ struct meson_sar_adc_param {
 	unsigned int				temperature_multiplier;
 	unsigned int				temperature_divider;
 	u8					disable_ring_counter;
+	bool					has_reg11;
+	bool					has_vref_select;
+	u8					vref_select;
+	u8					cmv_select;
+	u8					adc_eoc;
+	enum meson_sar_adc_vref_sel		vref_volatge;
 };
 
 struct meson_sar_adc_data {
@@ -974,6 +989,29 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 			   MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
 			   regval);
 
+	if (priv->param->has_reg11) {
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_EOC, regval);
+
+		if (priv->param->has_vref_select) {
+			regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,
+					    priv->param->vref_select);
+			regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+					   MESON_SAR_ADC_REG11_VREF_SEL, regval);
+		}
+
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
+				    priv->param->vref_volatge);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
+
+		regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
+				    priv->param->cmv_select);
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+				   MESON_SAR_ADC_REG11_CMV_SEL, regval);
+	}
+
 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
@@ -1195,6 +1233,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
 	.bandgap_reg = MESON_SAR_ADC_REG11,
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 10,
+	.has_reg11 = true,
+	.vref_volatge = 1,
+	.cmv_select = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
@@ -1204,6 +1245,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
 	.disable_ring_counter = 1,
+	.has_reg11 = true,
+	.vref_volatge = 1,
+	.cmv_select = 1,
 };
 
 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1213,6 +1257,10 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
 	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
 	.resolution = 12,
 	.disable_ring_counter = 1,
+	.has_reg11 = true,
+	.adc_eoc = 1,
+	.has_vref_select = true,
+	.vref_select = VREF_VDDA,
 };
 
 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
-- 
2.38.4


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Re: [PATCH v1 0/3] iio: adc: meson: tune init sequence

[Jonathan Cameron]

On Sat, 15 Jul 2023 14:05:57 +0300
George Stark <gnstark@sberdevices.ru> wrote:

> This patch is a part of effort to support meson a1 SoC and make meson saradc driver
> independent from vendor boot code initialization in common.
> 
> Information was taken from vendor kernel 5.4, 4.19 and vendor uboot 2019.
> Most of the bits are undocumented at all or it's not said how they affect measuring.
> 
> All those bits are already initialized in bl* code and since kernel driver dosn't
> rewrite or reset any registers but only changes some bits at init stage everything
> works fine.
> 
> Test procedure is rather simple - one can change those bits in runtime
> (e.g. using devmem) and try to read channels (cat /sys/bus/platform/drivers/meson-saradc/.../iio:device0/*)
> changing some of those bits leads to measure procedure errors or abnormal results.
> Another test is build meson saradc as module, reset adc by reset bit, reload module
> and compare measure results to those got before reset.
> 
> George Stark (3):
>   iio: adc: meson: init channels 0,1 input muxes
>   iio: adc: meson: init internal continuous ring counter
>   iio: adc: meson: init voltage control bits
> 
>  drivers/iio/adc/meson_saradc.c | 73 ++++++++++++++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
> 
These look fine to me, but I'd like them to sit on list a little while
on off chance anyone else has feedback on them.

Thanks,

Jonathan



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Re: [PATCH 1/3] iio: adc: meson: init channels 0,1 input muxes

[Markus Elfring]

> Set up input channels 0,1 muxes in the same way as for the channels 2-7
> later in the code.

Can a wording variant like “Set input channels “0,1 muxes” up …”
be a bit nicer?
(Is there a need to adjust any comments in the source code accordingly?)


Would you like to avoid empty descriptions according to addresses
in applied recipient lists?

Regards,
Markus

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Re: [PATCH 2/3] iio: adc: meson: init internal continuous ring counter

[Markus Elfring]

…
> This bit are inited in vendor boot code (bl2, bl33) already so do it
> in the driver to not depend on other code.

Can a wording variant (like the following) be nicer for the change description?


  These bits are initialised in vendor boot code (bl2, bl33) already.
  Thus do it in the driver to not depend on other code.


Regards,
Markus

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Re: [PATCH v1 0/3] iio: adc: meson: tune init sequence

[George Stark]

Hello Jonathan

Thanks for your review

On 7/16/23 19:11, Jonathan Cameron wrote:
> On Sat, 15 Jul 2023 14:05:57 +0300
> George Stark <gnstark@sberdevices.ru> wrote:
> 
>> This patch is a part of effort to support meson a1 SoC and make meson saradc driver
>> independent from vendor boot code initialization in common.
>>
>> Information was taken from vendor kernel 5.4, 4.19 and vendor uboot 2019.
>> Most of the bits are undocumented at all or it's not said how they affect measuring.
>>
>> All those bits are already initialized in bl* code and since kernel driver dosn't
>> rewrite or reset any registers but only changes some bits at init stage everything
>> works fine.
>>
>> Test procedure is rather simple - one can change those bits in runtime
>> (e.g. using devmem) and try to read channels (cat /sys/bus/platform/drivers/meson-saradc/.../iio:device0/*)
>> changing some of those bits leads to measure procedure errors or abnormal results.
>> Another test is build meson saradc as module, reset adc by reset bit, reload module
>> and compare measure results to those got before reset.
>>
>> George Stark (3):
>>    iio: adc: meson: init channels 0,1 input muxes
>>    iio: adc: meson: init internal continuous ring counter
>>    iio: adc: meson: init voltage control bits
>>
>>   drivers/iio/adc/meson_saradc.c | 73 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 73 insertions(+)
>>
> These look fine to me, but I'd like them to sit on list a little while
> on off chance anyone else has feedback on them.

I understand. I'd resend the patches in a week or more if there's no 
feedback.

If someone suggests tests so the community could trust the results I'll 
be happy to run them. I have odroid-c1, vim1, vim3 and a113l board.

> 
> Thanks,
> 
> Jonathan
> 
> 

-- 
Best regards
George

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Re: [PATCH v1 0/3] iio: adc: meson: tune init sequence

[Andy Shevchenko]

On Mon, Jul 17, 2023 at 12:41:29PM +0300, George Stark wrote:
> On 7/16/23 19:11, Jonathan Cameron wrote:
> > On Sat, 15 Jul 2023 14:05:57 +0300
> > George Stark <gnstark@sberdevices.ru> wrote:

...

> > These look fine to me, but I'd like them to sit on list a little while
> > on off chance anyone else has feedback on them.
> 
> I understand. I'd resend the patches in a week or more if there's no
> feedback.

There is no need to resend as long as they are available via lore.kernel.org
mail archives.

-- 
With Best Regards,
Andy Shevchenko



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Re: [PATCH v1 0/3] iio: adc: meson: tune init sequence

[Jonathan Cameron]

On Mon, 17 Jul 2023 13:01:09 +0300
Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:

> On Mon, Jul 17, 2023 at 12:41:29PM +0300, George Stark wrote:
> > On 7/16/23 19:11, Jonathan Cameron wrote:  
> > > On Sat, 15 Jul 2023 14:05:57 +0300
> > > George Stark <gnstark@sberdevices.ru> wrote:  
> 
> ...
> 
> > > These look fine to me, but I'd like them to sit on list a little while
> > > on off chance anyone else has feedback on them.  
> > 
> > I understand. I'd resend the patches in a week or more if there's no
> > feedback.  
> 
> There is no need to resend as long as they are available via lore.kernel.org
> mail archives.
> 

FYI, I track using patchwork.kernel.org so rarely drop a patch set down the back of the
sofa any more...

Jonathan

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Re: [PATCH v1 0/3] iio: adc: meson: tune init sequence

[Jonathan Cameron]

On Tue, 18 Jul 2023 10:41:00 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Mon, 17 Jul 2023 13:01:09 +0300
> Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> 
> > On Mon, Jul 17, 2023 at 12:41:29PM +0300, George Stark wrote:  
> > > On 7/16/23 19:11, Jonathan Cameron wrote:    
> > > > On Sat, 15 Jul 2023 14:05:57 +0300
> > > > George Stark <gnstark@sberdevices.ru> wrote:    
> > 
> > ...
> >   
> > > > These look fine to me, but I'd like them to sit on list a little while
> > > > on off chance anyone else has feedback on them.    
> > > 
> > > I understand. I'd resend the patches in a week or more if there's no
> > > feedback.    
> > 
> > There is no need to resend as long as they are available via lore.kernel.org
> > mail archives.
> >   
> 
> FYI, I track using patchwork.kernel.org so rarely drop a patch set down the back of the
> sofa any more...
> 
> Jonathan

Long enough.  Applied to the togreg branch of iio.git and pushed out as testing
for 0-day to see if we missed anything.

Thanks,

Jonathan



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