Re: [PATCH v2 1/2] iio: adc: meson: fix core clock enable/disable moment

From: Jonathan Cameron <jic23@kernel.org>
To: George Stark <gnstark@sberdevices.ru>
Cc: <lars@metafoo.de>, <neil.armstrong@linaro.org>,
	<khilman@baylibre.com>, <jbrunet@baylibre.com>,
	<martin.blumenstingl@googlemail.com>,
	<andriy.shevchenko@linux.intel.com>, <nuno.sa@analog.com>,
	<linux-iio@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-amlogic@lists.infradead.org>, <kernel@sberdevices.ru>
Subject: Re: [PATCH v2 1/2] iio: adc: meson: fix core clock enable/disable moment
Date: Sat, 22 Jul 2023 18:13:45 +0100	[thread overview]
Message-ID: <20230722181345.44a79b6d@jic23-huawei> (raw)
In-Reply-To: <20230721102413.255726-2-gnstark@sberdevices.ru>

On Fri, 21 Jul 2023 13:23:08 +0300
George Stark <gnstark@sberdevices.ru> wrote:

> Enable core clock at probe stage and disable it at remove stage.
> Core clock is responsible for turning on/off the entire SoC module so
> it should be on before the first module register is touched and be off
> at very last moment.
> 
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <gnstark@sberdevices.ru>
Applied to the fixes-togreg branch of iio.git and marked for stable.

The 2nd patch will have to wait as it's not a fix.

Thanks,

Jonathan
> ---
>  drivers/iio/adc/meson_saradc.c | 23 ++++++++++++-----------
>  1 file changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> index 2ee12f3ad312..8397a5347f32 100644
> --- a/drivers/iio/adc/meson_saradc.c
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -1055,12 +1055,6 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
>  		goto err_vref;
>  	}
>  
> -	ret = clk_prepare_enable(priv->core_clk);
> -	if (ret) {
> -		dev_err(dev, "failed to enable core clk\n");
> -		goto err_core_clk;
> -	}
> -
>  	regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
>  	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
>  			   MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
> @@ -1087,8 +1081,6 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
>  	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
>  			   MESON_SAR_ADC_REG3_ADC_EN, 0);
>  	meson_sar_adc_set_bandgap(indio_dev, false);
> -	clk_disable_unprepare(priv->core_clk);
> -err_core_clk:
>  	regulator_disable(priv->vref);
>  err_vref:
>  	meson_sar_adc_unlock(indio_dev);
> @@ -1116,8 +1108,6 @@ static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
>  
>  	meson_sar_adc_set_bandgap(indio_dev, false);
>  
> -	clk_disable_unprepare(priv->core_clk);
> -
>  	regulator_disable(priv->vref);
>  
>  	if (!ret)
> @@ -1379,7 +1369,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->clkin))
>  		return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
>  
> -	priv->core_clk = devm_clk_get(dev, "core");
> +	priv->core_clk = devm_clk_get_enabled(dev, "core");
>  	if (IS_ERR(priv->core_clk))
>  		return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
>  
> @@ -1462,15 +1452,26 @@ static int meson_sar_adc_remove(struct platform_device *pdev)
>  static int meson_sar_adc_suspend(struct device *dev)
>  {
>  	struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +	struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
>  
>  	meson_sar_adc_hw_disable(indio_dev);
>  
> +	clk_disable_unprepare(priv->core_clk);
> +
>  	return 0;
>  }
>  
>  static int meson_sar_adc_resume(struct device *dev)
>  {
>  	struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +	struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +	int ret;
> +
> +	ret = clk_prepare_enable(priv->core_clk);
> +	if (ret) {
> +		dev_err(dev, "failed to enable core clk\n");
> +		return ret;
> +	}
>  
>  	return meson_sar_adc_hw_enable(indio_dev);
>  }

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