From: Elaine Zhang <zhangqing@rock-chips.com>
To: mturquette@baylibre.com, sboyd@kernel.org,
kever.yang@rock-chips.com, zhangqing@rock-chips.com,
heiko@sntech.de, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, huangtao@rock-chips.com
Subject: [RESEND PATCH v3 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id
Date: Fri, 4 Aug 2023 10:51:01 +0800 [thread overview]
Message-ID: <20230804025101.28438-1-zhangqing@rock-chips.com> (raw)
add PCLK_VO1GRF clk id.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h
index b5616bca7b44..864a321ab362 100644
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
@@ -733,8 +733,9 @@
#define ACLK_AV1_PRE 718
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
+#define PCLK_VO1GRF 721
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+#define CLK_NR_CLKS (PCLK_VO1GRF + 1)
/* scmi-clocks indices */
--
2.17.1
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next reply other threads:[~2023-08-04 2:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-04 2:51 Elaine Zhang [this message]
2023-08-04 15:38 ` [RESEND PATCH v3 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Conor Dooley
2023-08-07 8:41 ` Krzysztof Kozlowski
-- strict thread matches above, loose matches on Subject: below --
2023-08-07 6:59 [RESEND PATCH v3 0/4] rockchip: add GATE_LINK Elaine Zhang
2023-08-07 6:59 ` [RESEND PATCH v3 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang
2023-08-07 8:41 ` Krzysztof Kozlowski
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