From: Shawn Guo <shawnguo@kernel.org>
To: Hui Wang <hui.wang@canonical.com>
Cc: linux-arm-kernel@lists.infradead.org, leoyang.li@nxp.com,
s.hauer@pengutronix.de
Subject: Re: [PATCH] arm64: dts: ls1028a: add l1 and l2 cache info
Date: Sun, 6 Aug 2023 20:18:05 +0800 [thread overview]
Message-ID: <20230806121805.GD151430@dragon> (raw)
In-Reply-To: <20230731084614.59785-1-hui.wang@canonical.com>
On Mon, Jul 31, 2023 at 04:46:14PM +0800, Hui Wang wrote:
> When we ran the stress-ng cache related stressors, we got the log as
> below:
> ubuntu@ubuntu:~$ stress-ng --l1cache 4
> stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
> stress-ng: info: [656] dispatching hogs: 4 l1cache
> stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel
>
> This is because the l1 and l2 cache info is missing in the devicetree,
> ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
> 1MB l2 ucache:
> - icache is 3-way set associative
> - dcache is 2-way set associative
> - l2cache is 16-way set associative
> - line size are 64bytes
>
> Signed-off-by: Hui Wang <hui.wang@canonical.com>
Applied, thanks!
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prev parent reply other threads:[~2023-08-06 12:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-31 8:46 [PATCH] arm64: dts: ls1028a: add l1 and l2 cache info Hui Wang
2023-08-06 12:18 ` Shawn Guo [this message]
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