* [PATCH] net: stmmac: xgmac: RX queue routing configuration
@ 2023-08-07 6:56 Furong Xu
2023-08-07 15:18 ` Simon Horman
0 siblings, 1 reply; 2+ messages in thread
From: Furong Xu @ 2023-08-07 6:56 UTC (permalink / raw)
To: David S. Miller, Alexandre Torgue, Jose Abreu, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Joao Pinto
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, xfr, rock.xu,
Furong Xu
Commit abe80fdc6ee6 ("net: stmmac: RX queue routing configuration")
introduced RX queue routing to DWMAC4 core.
This patch extend the support to XGMAC2 core.
Signed-off-by: Furong Xu <0x1207@gmail.com>
---
.../net/ethernet/stmicro/stmmac/dwxgmac2.h | 14 +++++++
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 37 ++++++++++++++++++-
2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 1913385df685..a2498da7406b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -74,8 +74,22 @@
#define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
#define XGMAC_RXQEN_SHIFT(x) ((x) * 2)
#define XGMAC_RXQ_CTRL1 0x000000a4
+#define XGMAC_AVCPQ GENMASK(31, 28)
+#define XGMAC_AVCPQ_SHIFT 28
+#define XGMAC_PTPQ GENMASK(27, 24)
+#define XGMAC_PTPQ_SHIFT 24
+#define XGMAC_TACPQE BIT(23)
+#define XGMAC_TACPQE_SHIFT 23
+#define XGMAC_DCBCPQ GENMASK(19, 16)
+#define XGMAC_DCBCPQ_SHIFT 16
+#define XGMAC_MCBCQEN BIT(15)
+#define XGMAC_MCBCQEN_SHIFT 15
+#define XGMAC_MCBCQ GENMASK(11, 8)
+#define XGMAC_MCBCQ_SHIFT 8
#define XGMAC_RQ GENMASK(7, 4)
#define XGMAC_RQ_SHIFT 4
+#define XGMAC_UPQ GENMASK(3, 0)
+#define XGMAC_UPQ_SHIFT 0
#define XGMAC_RXQ_CTRL2 0x000000a8
#define XGMAC_RXQ_CTRL3 0x000000ac
#define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index a0c2ef8bb0ac..24918d95f612 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -127,6 +127,39 @@ static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
writel(value, ioaddr + reg);
}
+static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,
+ u8 packet, u32 queue)
+{
+ void __iomem *ioaddr = hw->pcsr;
+ u32 value;
+
+ static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {
+ { XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },
+ { XGMAC_PTPQ, XGMAC_PTPQ_SHIFT },
+ { XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT },
+ { XGMAC_UPQ, XGMAC_UPQ_SHIFT },
+ { XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT },
+ };
+
+ value = readl(ioaddr + XGMAC_RXQ_CTRL1);
+
+ /* routing configuration */
+ value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
+ value |= (queue << dwxgmac2_route_possibilities[packet-1].reg_shift) &
+ dwxgmac2_route_possibilities[packet - 1].reg_mask;
+
+ /* some packets require extra ops */
+ if (packet == PACKET_AVCPQ) {
+ value &= ~XGMAC_TACPQE;
+ value |= 0x1 << XGMAC_TACPQE_SHIFT;
+ } else if (packet == PACKET_MCBCQ) {
+ value &= ~XGMAC_MCBCQEN;
+ value |= 0x1 << XGMAC_MCBCQEN_SHIFT;
+ }
+
+ writel(value, ioaddr + XGMAC_RXQ_CTRL1);
+}
+
static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
u32 rx_alg)
{
@@ -1463,7 +1496,7 @@ const struct stmmac_ops dwxgmac210_ops = {
.rx_queue_enable = dwxgmac2_rx_queue_enable,
.rx_queue_prio = dwxgmac2_rx_queue_prio,
.tx_queue_prio = dwxgmac2_tx_queue_prio,
- .rx_queue_routing = NULL,
+ .rx_queue_routing = dwxgmac2_rx_queue_routing,
.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
@@ -1524,7 +1557,7 @@ const struct stmmac_ops dwxlgmac2_ops = {
.rx_queue_enable = dwxlgmac2_rx_queue_enable,
.rx_queue_prio = dwxgmac2_rx_queue_prio,
.tx_queue_prio = dwxgmac2_tx_queue_prio,
- .rx_queue_routing = NULL,
+ .rx_queue_routing = dwxgmac2_rx_queue_routing,
.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
--
2.34.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] net: stmmac: xgmac: RX queue routing configuration
2023-08-07 6:56 [PATCH] net: stmmac: xgmac: RX queue routing configuration Furong Xu
@ 2023-08-07 15:18 ` Simon Horman
0 siblings, 0 replies; 2+ messages in thread
From: Simon Horman @ 2023-08-07 15:18 UTC (permalink / raw)
To: Furong Xu
Cc: David S. Miller, Alexandre Torgue, Jose Abreu, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Joao Pinto, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, xfr, rock.xu
On Mon, Aug 07, 2023 at 02:56:09PM +0800, Furong Xu wrote:
> Commit abe80fdc6ee6 ("net: stmmac: RX queue routing configuration")
> introduced RX queue routing to DWMAC4 core.
> This patch extend the support to XGMAC2 core.
>
> Signed-off-by: Furong Xu <0x1207@gmail.com>
Hi Furong Xu,
as this is a feature for a Networking it (probably) should
be targeted at net-next - as opposed to net, which is for bug fixes.
The target tree should be included in the subject.
Subject: [PATCH net-next] ...
...
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> index a0c2ef8bb0ac..24918d95f612 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> @@ -127,6 +127,39 @@ static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
> writel(value, ioaddr + reg);
> }
>
> +static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,
> + u8 packet, u32 queue)
> +{
> + void __iomem *ioaddr = hw->pcsr;
> + u32 value;
> +
> + static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {
> + { XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },
> + { XGMAC_PTPQ, XGMAC_PTPQ_SHIFT },
> + { XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT },
> + { XGMAC_UPQ, XGMAC_UPQ_SHIFT },
> + { XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT },
> + };
> +
> + value = readl(ioaddr + XGMAC_RXQ_CTRL1);
> +
> + /* routing configuration */
> + value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
> + value |= (queue << dwxgmac2_route_possibilities[packet-1].reg_shift) &
> + dwxgmac2_route_possibilities[packet - 1].reg_mask;
> +
> + /* some packets require extra ops */
> + if (packet == PACKET_AVCPQ) {
> + value &= ~XGMAC_TACPQE;
> + value |= 0x1 << XGMAC_TACPQE_SHIFT;
FIELD_PREP seems appropriate here.
> + } else if (packet == PACKET_MCBCQ) {
> + value &= ~XGMAC_MCBCQEN;
> + value |= 0x1 << XGMAC_MCBCQEN_SHIFT;
And here.
> + }
> +
> + writel(value, ioaddr + XGMAC_RXQ_CTRL1);
> +}
> +
> static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
> u32 rx_alg)
> {
...
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