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Mon, 7 Aug 2023 10:42:08 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 7 Aug 2023 10:42:07 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 7 Aug 2023 10:42:07 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 377Fg73T091750; Mon, 7 Aug 2023 10:42:07 -0500 Date: Mon, 7 Aug 2023 10:42:07 -0500 From: Nishanth Menon To: Andrew Davis CC: Dhruva Gole , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , Subject: Re: [PATCH 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Message-ID: <20230807154207.7eho6er55revipjo@shuffling> References: <20230802205309.257392-1-afd@ti.com> <20230802205309.257392-11-afd@ti.com> <1b3366b0-e3a4-3609-9e25-7b880d2fe656@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1b3366b0-e3a4-3609-9e25-7b880d2fe656@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230807_084216_121526_B22C7D4C X-CRM114-Status: GOOD ( 26.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10:28-20230807, Andrew Davis wrote: > On 8/7/23 12:38 AM, Dhruva Gole wrote: > > Andrew, > > = > > On 03/08/23 02:23, Andrew Davis wrote: > > > GPIO nodes defined in the top-level J7200 SoC dtsi files are incomple= te > > > and may not be functional unless they are extended with pinmux and > > > device information. > > > = > > > Disable the GPIO nodes in the dtsi files and only enable the ones that > > > are actually pinned out on a given board. > > > = > > > Signed-off-by: Andrew Davis > > > --- > > > =A0 .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++---------= ----- > > > =A0 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi=A0=A0=A0=A0=A0 |=A0 4 += +++ > > > =A0 .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi |=A0 2 ++ > > > =A0 3 files changed, 10 insertions(+), 14 deletions(-) > > > = > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/= arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > index dee9056f56051..4a5c4f36baeec 100644 > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > @@ -240,27 +240,17 @@ &main_uart3 { > > > =A0=A0=A0=A0=A0 pinctrl-0 =3D <&main_uart3_pins_default>; > > > =A0 }; > > > -&main_gpio2 { > > > -=A0=A0=A0 status =3D "disabled"; > > > -}; > > > - > > > -&main_gpio4 { > > > -=A0=A0=A0 status =3D "disabled"; > > > -}; > > > - > > > -&main_gpio6 { > > > -=A0=A0=A0 status =3D "disabled"; > > > +&main_gpio0 { > > > +=A0=A0=A0 status =3D "okay"; > > > +=A0=A0=A0 /* default pins */ > > = > > Small question, where is the pmx for main_gpio0? What does "default pin= s" > > refer to here? Where are they pinmuxed? > > = > = > Good question, where is the pmx for main_gpio0? I don't know, it was > never defined before either, we only are noticing this now as we are > disabling by default instead of leaving an unfinished node enabled > by default. (another benefit of this disabled by default scheme). > = > What is really happening is GPIO nodes we tend to pinmux differently > than normal device nodes. Their pinmux selections tends to be spread > out in all the nodes that make use of these GPIO pins, not all together > here in this node. > = > For instance in this device we use one of the main_gpio0 pins as a > GPIO toggled regulator, and we define the pinmux for it in that node > (see vdd-sd-dv-default-pins). > = > We can either define the rest of the pins not used elsewhere > here, or we can consider GPIO an exception to the rule, I'd say > the latter is fine for now. GPIO pinmux are typically defined where they need - the only place where they are explicitly called out in gpio is when they are meant to be used by libgpio - typically in the case of dev boards. Just drop the comments of /* default pins */ - that is just mis-leading. -- = Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5= 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel