Re: [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support

Re: [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support

[Conor Dooley]

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On Wed, Jul 26, 2023 at 05:02:23PM +0200, Herve Codina wrote:
> A framer can be connected to the QMC HDLC.
> If present, this framer is the interface between the TDM used by the QMC
> HDLC and the E1/T1 line.
> The QMC HDLC can use this framer to get information about the line and
> configure the line.
> 
> Add an optional framer property to reference the framer itself.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Why not fully describe the hardware in one patch in this series, rather
than split this over two different ones?

> ---
>  Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> index 8bb6f34602d9..bf29863ab419 100644
> --- a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> @@ -27,6 +27,11 @@ properties:
>        Should be a phandle/number pair. The phandle to QMC node and the QMC
>        channel to use.
>  
> +  framer:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      phandle to the framer node
> +
>  required:
>    - compatible
>    - fsl,qmc-chan
> -- 
> 2.41.0
> 

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Re: [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support

[Herve Codina]

Hi Conor,

On Thu, 27 Jul 2023 09:12:01 +0100
Conor Dooley <conor@kernel.org> wrote:

> On Wed, Jul 26, 2023 at 05:02:23PM +0200, Herve Codina wrote:
> > A framer can be connected to the QMC HDLC.
> > If present, this framer is the interface between the TDM used by the QMC
> > HDLC and the E1/T1 line.
> > The QMC HDLC can use this framer to get information about the line and
> > configure the line.
> > 
> > Add an optional framer property to reference the framer itself.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>  
> 
> Why not fully describe the hardware in one patch in this series, rather
> than split this over two different ones?

I agree, this can be squashed with a previous commit.
My intention was to keep things separated in this first series.

The framer property makes sense only if the stuff related the generic framer
(previous patches) are accepted whereas the QMC HDLC previous binding can be
accepted without this framer property.
I though it would be easier to review the full series with separated
modifications.

That's said, I will squash this patch with the patch 5 ("dt-bindings: net:
Add support for QMC HDLC") in the next iteration.

Best regards,
Hervé

> 
> > ---
> >  Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > index 8bb6f34602d9..bf29863ab419 100644
> > --- a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > @@ -27,6 +27,11 @@ properties:
> >        Should be a phandle/number pair. The phandle to QMC node and the QMC
> >        channel to use.
> >  
> > +  framer:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      phandle to the framer node
> > +
> >  required:
> >    - compatible
> >    - fsl,qmc-chan
> > -- 
> > 2.41.0
> >   

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Re: [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support

[Rob Herring]

On Wed, Jul 26, 2023 at 05:02:23PM +0200, Herve Codina wrote:
> A framer can be connected to the QMC HDLC.
> If present, this framer is the interface between the TDM used by the QMC
> HDLC and the E1/T1 line.
> The QMC HDLC can use this framer to get information about the line and
> configure the line.
> 
> Add an optional framer property to reference the framer itself.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> index 8bb6f34602d9..bf29863ab419 100644
> --- a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> @@ -27,6 +27,11 @@ properties:
>        Should be a phandle/number pair. The phandle to QMC node and the QMC
>        channel to use.
>  
> +  framer:
> +    $ref: /schemas/types.yaml#/definitions/phandle

Now you've defined this property twice. Please avoid doing that.

> +    description:
> +      phandle to the framer node
> +
>  required:
>    - compatible
>    - fsl,qmc-chan
> -- 
> 2.41.0
> 

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Re: [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support

[Herve Codina]

Hi Rob,

On Wed, 2 Aug 2023 18:42:59 -0600
Rob Herring <robh@kernel.org> wrote:

> On Wed, Jul 26, 2023 at 05:02:23PM +0200, Herve Codina wrote:
> > A framer can be connected to the QMC HDLC.
> > If present, this framer is the interface between the TDM used by the QMC
> > HDLC and the E1/T1 line.
> > The QMC HDLC can use this framer to get information about the line and
> > configure the line.
> > 
> > Add an optional framer property to reference the framer itself.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > index 8bb6f34602d9..bf29863ab419 100644
> > --- a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > @@ -27,6 +27,11 @@ properties:
> >        Should be a phandle/number pair. The phandle to QMC node and the QMC
> >        channel to use.
> >  
> > +  framer:
> > +    $ref: /schemas/types.yaml#/definitions/phandle  
> 
> Now you've defined this property twice. Please avoid doing that.

I don't see what you mean.

I previously defined the framer property at the framer-codec node as it is
a framer consumer (it was a mistake because this framer-codec node is a child of
the framer node but that's an other story).

Here, at the qmc-hdlc node, I define this property in order to use the framer as a
consumer too.

What is wrong ?

Best regards,
Hervé

> 
> > +    description:
> > +      phandle to the framer node
> > +
> >  required:
> >    - compatible
> >    - fsl,qmc-chan
> > -- 
> > 2.41.0
> >   

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Re: [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC

[Conor Dooley]

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On Wed, Jul 26, 2023 at 05:02:01PM +0200, Herve Codina wrote:
> The QMC (QUICC mutichannel controller) is a controller present in some
> PowerQUICC SoC such as MPC885.
> The QMC HDLC uses the QMC controller to transfer HDLC data.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  .../devicetree/bindings/net/fsl,qmc-hdlc.yaml | 41 +++++++++++++++++++
>  1 file changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> new file mode 100644
> index 000000000000..8bb6f34602d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/fsl,qmc-hdlc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: QMC HDLC

"QMC HDLC" seems excessively terse.

> +
> +maintainers:
> +  - Herve Codina <herve.codina@bootlin.com>
> +
> +description: |
> +  The QMC HDLC uses a QMC (QUICC Multichannel Controller) channel to transfer
> +  HDLC data.
> +
> +properties:
> +  compatible:
> +    const: fsl,qmc-hdlc
> +
> +  fsl,qmc-chan:

Perhaps I am just showing my lack of knowledge in this area, but what is
fsl specific about wanting a reference to the channel of a "QMC"?
Is this something that hardware from other manufacturers would not also
want to do?

> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to QMC node
> +          - description: Channel number
> +    description:
> +      Should be a phandle/number pair. The phandle to QMC node and the QMC
> +      channel to use.
> +
> +required:
> +  - compatible
> +  - fsl,qmc-chan
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    hdlc {
> +        compatible = "fsl,qmc-hdlc";
> +        fsl,qmc-chan = <&qmc 16>;
> +    };
> -- 
> 2.41.0
> 

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Re: [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC

[Herve Codina]

Hi Conor,

On Thu, 27 Jul 2023 09:19:59 +0100
Conor Dooley <conor@kernel.org> wrote:

> On Wed, Jul 26, 2023 at 05:02:01PM +0200, Herve Codina wrote:
> > The QMC (QUICC mutichannel controller) is a controller present in some
> > PowerQUICC SoC such as MPC885.
> > The QMC HDLC uses the QMC controller to transfer HDLC data.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  .../devicetree/bindings/net/fsl,qmc-hdlc.yaml | 41 +++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > new file mode 100644
> > index 000000000000..8bb6f34602d9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/fsl,qmc-hdlc.yaml
> > @@ -0,0 +1,41 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/fsl,qmc-hdlc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: QMC HDLC  
> 
> "QMC HDLC" seems excessively terse.

The name was based on the fsl,qmc-audio.yaml already present upstream.
  https://elixir.bootlin.com/linux/v6.4/source/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml

If needed, I can change to:
  title: QMC (QUICC Multichannel Controller) HDLC
Let me known if it is better to you.

> 
> > +
> > +maintainers:
> > +  - Herve Codina <herve.codina@bootlin.com>
> > +
> > +description: |
> > +  The QMC HDLC uses a QMC (QUICC Multichannel Controller) channel to transfer
> > +  HDLC data.
> > +
> > +properties:
> > +  compatible:
> > +    const: fsl,qmc-hdlc
> > +
> > +  fsl,qmc-chan:  
> 
> Perhaps I am just showing my lack of knowledge in this area, but what is
> fsl specific about wanting a reference to the channel of a "QMC"?
> Is this something that hardware from other manufacturers would not also
> want to do?

The QMC and the QMC channel are something specific to the SoC. This IP is only
available on some Freescale/NXP SoCs.

When I upstreamed the 'fsl,qmc-audio.yaml', I first used a generic name for this
property and Kristoff asked to change to a vendor prefixed name.
  https://lore.kernel.org/linux-kernel/1dfade07-f8c4-2e16-00dc-c7d183708259@linaro.org/

Based on this, as the property 'fsl,qmc-chan' has the exact same meaning in
fsl,qmc-audio.yaml and fsl,qmc-hdlc.yaml, I use the same name.

Best regards,
Hervé

> 
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      - items:
> > +          - description: phandle to QMC node
> > +          - description: Channel number
> > +    description:
> > +      Should be a phandle/number pair. The phandle to QMC node and the QMC
> > +      channel to use.
> > +
> > +required:
> > +  - compatible
> > +  - fsl,qmc-chan
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    hdlc {
> > +        compatible = "fsl,qmc-hdlc";
> > +        fsl,qmc-chan = <&qmc 16>;
> > +    };
> > -- 
> > 2.41.0
> >   

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Re: [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC

[Conor Dooley]

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On Thu, Jul 27, 2023 at 11:09:48AM +0200, Herve Codina wrote:
> On Thu, 27 Jul 2023 09:19:59 +0100
> Conor Dooley <conor@kernel.org> wrote:
> > On Wed, Jul 26, 2023 at 05:02:01PM +0200, Herve Codina wrote:

> If needed, I can change to:
>   title: QMC (QUICC Multichannel Controller) HDLC
> Let me known if it is better to you.

If it were me writing the binding, I'd probably use something like
"Freescale/NXP QUICC Multichannel Controller (QMC) HDLC", but it is not
a big deal, I just had a "wtf is this" moment :)



> > > +  fsl,qmc-chan:
> > 
> > Perhaps I am just showing my lack of knowledge in this area, but what is
> > fsl specific about wanting a reference to the channel of a "QMC"?
> > Is this something that hardware from other manufacturers would not also
> > want to do?
> 
> The QMC and the QMC channel are something specific to the SoC. This IP is only
> available on some Freescale/NXP SoCs.
> 
> When I upstreamed the 'fsl,qmc-audio.yaml', I first used a generic name for this
> property and Kristoff asked to change to a vendor prefixed name.
>   https://lore.kernel.org/linux-kernel/1dfade07-f8c4-2e16-00dc-c7d183708259@linaro.org/
> 
> Based on this, as the property 'fsl,qmc-chan' has the exact same meaning in
> fsl,qmc-audio.yaml and fsl,qmc-hdlc.yaml, I use the same name.

Okay, thanks for explaining!

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Re: [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC

[Herve Codina]

Hi Conor,

On Thu, 27 Jul 2023 10:53:15 +0100
Conor Dooley <conor@kernel.org> wrote:

> On Thu, Jul 27, 2023 at 11:09:48AM +0200, Herve Codina wrote:
> > On Thu, 27 Jul 2023 09:19:59 +0100
> > Conor Dooley <conor@kernel.org> wrote:  
> > > On Wed, Jul 26, 2023 at 05:02:01PM +0200, Herve Codina wrote:  
> 
> > If needed, I can change to:
> >   title: QMC (QUICC Multichannel Controller) HDLC
> > Let me known if it is better to you.  
> 
> If it were me writing the binding, I'd probably use something like
> "Freescale/NXP QUICC Multichannel Controller (QMC) HDLC", but it is not
> a big deal, I just had a "wtf is this" moment :)

I will change to "Freescale/NXP QUICC Multichannel Controller (QMC) HDLC" in
the next iteration.

> 
> 
> 
> > > > +  fsl,qmc-chan:  
> > > 
> > > Perhaps I am just showing my lack of knowledge in this area, but what is
> > > fsl specific about wanting a reference to the channel of a "QMC"?
> > > Is this something that hardware from other manufacturers would not also
> > > want to do?  
> > 
> > The QMC and the QMC channel are something specific to the SoC. This IP is only
> > available on some Freescale/NXP SoCs.
> > 
> > When I upstreamed the 'fsl,qmc-audio.yaml', I first used a generic name for this
> > property and Kristoff asked to change to a vendor prefixed name.
> >   https://lore.kernel.org/linux-kernel/1dfade07-f8c4-2e16-00dc-c7d183708259@linaro.org/
> > 
> > Based on this, as the property 'fsl,qmc-chan' has the exact same meaning in
> > fsl,qmc-audio.yaml and fsl,qmc-hdlc.yaml, I use the same name.  
> 
> Okay, thanks for explaining!

You're welcome.

Regards,
Hervé


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Re: [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

[Andrew Lunn]

> +  clocks:
> +    items:
> +      - description: Master clock
> +      - description: Receive System Clock
> +      - description: Transmit System Clock
> +
> +  clock-names:
> +    items:
> +      - const: mclk
> +      - const: sclkr
> +      - const: sclkx

Nit pick, but "Receive System Clock", but "sclkr'. Maybe "System Clock
Receive" so you have the same word order?

	 Andrew

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Re: [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

[Herve Codina]

On Tue, 1 Aug 2023 12:05:07 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > +  clocks:
> > +    items:
> > +      - description: Master clock
> > +      - description: Receive System Clock
> > +      - description: Transmit System Clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: mclk
> > +      - const: sclkr
> > +      - const: sclkx  
> 
> Nit pick, but "Receive System Clock", but "sclkr'. Maybe "System Clock
> Receive" so you have the same word order?
> 

Will also change the 'Transmit System Clock' to 'System Clock Transmit'

Regards,
Hervé



-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

[Rob Herring]

On Wed, Jul 26, 2023 at 05:02:17PM +0200, Herve Codina wrote:
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  .../bindings/net/lantiq,pef2256.yaml          | 226 ++++++++++++++++++
>  1 file changed, 226 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> new file mode 100644
> index 000000000000..b369a20d61b1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> @@ -0,0 +1,226 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lantiq PEF2256
> +
> +maintainers:
> +  - Herve Codina <herve.codina@bootlin.com>
> +
> +description:
> +  The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer and
> +  line interface component designed to fulfill all required interfacing between
> +  an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: lantiq,pef2256
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Master clock
> +      - description: Receive System Clock
> +      - description: Transmit System Clock
> +
> +  clock-names:
> +    items:
> +      - const: mclk
> +      - const: sclkr
> +      - const: sclkx
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  reset-gpios:
> +    description:
> +      GPIO used to reset the device.
> +    maxItems: 1
> +
> +  '#framer-cells':

Looks generic, but no such property is defined. You don't need something 
like this unless there are multiple providers and you need each 
provider to define the number of cells.

> +    const: 0
> +
> +  pinctrl:
> +    $ref: /schemas/pinctrl/pinctrl.yaml#
> +    additionalProperties: false
> +
> +    patternProperties:
> +      '-pins$':
> +        type: object
> +        $ref: /schemas/pinctrl/pincfg-node.yaml#
> +        additionalProperties: false
> +
> +        properties:
> +          pins:
> +            enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
> +
> +          function:
> +            enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
> +                    SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
> +                    GPI, GPOH, GPOL ]
> +
> +        required:
> +          - pins
> +          - function
> +
> +  lantiq,data-rate-bps:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [2048000, 4096000, 8192000, 16384000]
> +    default: 2048000
> +    description:
> +      Data rate (bit per seconds) on the system highway.
> +
> +  lantiq,clock-falling-edge:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      Data is sent on falling edge of the clock (and received on the rising
> +      edge). If 'clock-falling-edge' is not present, data is sent on the
> +      rising edge (and received on the falling edge).
> +
> +  lantiq,channel-phase:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +    default: 0
> +    description:
> +      The pef2256 delivers a full frame (32 8bit time-slots in E1 and 24 8bit
> +      time-slots 8 8bit signaling in E1/J1) every 125us. This lead to a data
> +      rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
> +      bit/s, the data (all 32 8bit) present in the frame are interleave with
> +      unused time-slots. The lantiq,channel-phase property allows to set the
> +      correct alignment of the interleave mechanism.
> +      For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
> +      lantiq,channel-phase = 2, the interleave schema with unused time-slots
> +      (nu) and used time-slots (XX) for TSi is
> +        nu nu XX nu nu nu XX nu nu nu XX nu
> +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +      With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
> +      interleave schema is
> +        nu XX nu nu nu XX nu nu nu XX nu nu
> +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +      With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
> +      lantiq,channel-phase = 1, the interleave schema is
> +        nu    XX    nu    XX    nu    XX
> +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +
> +patternProperties:
> +  '^codec(-([0-9]|[1-2][0-9]|3[0-1]))?$':
> +    type: object
> +    $ref: /schemas/sound/dai-common.yaml
> +    unevaluatedProperties: false
> +    description:
> +      Codec provided by the pef2256. This codec allows to use some of the PCM
> +      system highway time-slots as audio channels to transport audio data over
> +      the E1/T1/J1 lines.
> +      The time-slots used by the codec must be set and so, the properties
> +      'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
> +      'dai-tdm-slot-rx-mask' must be present in the sound card node for
> +      sub-nodes that involve the codec. The codec uses 8bit time-slots.
> +      'dai-tdm-tdm-slot-with' must be set to 8.
> +      The tx and rx masks define the pef2256 time-slots assigned to the codec.
> +
> +    properties:
> +      compatible:
> +        const: lantiq,pef2256-codec
> +
> +      '#sound-dai-cells':
> +        const: 0
> +
> +      framer:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description:
> +          phandle to the framer node

That's just the parent. Why do you need this?

Rob


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Re: [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

[Herve Codina]

Hi Rob,

On Wed, 2 Aug 2023 18:40:54 -0600
Rob Herring <robh@kernel.org> wrote:

> On Wed, Jul 26, 2023 at 05:02:17PM +0200, Herve Codina wrote:
> > The Lantiq PEF2256 is a framer and line interface component designed to
> > fulfill all required interfacing between an analog E1/T1/J1 line and the
> > digital PCM system highway/H.100 bus.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  .../bindings/net/lantiq,pef2256.yaml          | 226 ++++++++++++++++++
> >  1 file changed, 226 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > new file mode 100644
> > index 000000000000..b369a20d61b1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > @@ -0,0 +1,226 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Lantiq PEF2256
> > +
> > +maintainers:
> > +  - Herve Codina <herve.codina@bootlin.com>
> > +
> > +description:
> > +  The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer and
> > +  line interface component designed to fulfill all required interfacing between
> > +  an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: lantiq,pef2256
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Master clock
> > +      - description: Receive System Clock
> > +      - description: Transmit System Clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: mclk
> > +      - const: sclkr
> > +      - const: sclkx
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  reset-gpios:
> > +    description:
> > +      GPIO used to reset the device.
> > +    maxItems: 1
> > +
> > +  '#framer-cells':  
> 
> Looks generic, but no such property is defined. You don't need something 
> like this unless there are multiple providers and you need each 
> provider to define the number of cells.

With the framer infrastructure introduced in this series, multiple providers
can be present. Some framer chips are dual or quad framers.

With this pef2256 framer provider, consumers use "framer = <&pef2256>;"
but with some others framer provider, we can have "framer = <&foo 1>;"

That's the reason why I set '#framer-cells' in this first framer provider,
even if the value is 0.

> 
> > +    const: 0
> > +
> > +  pinctrl:
> > +    $ref: /schemas/pinctrl/pinctrl.yaml#
> > +    additionalProperties: false
> > +
> > +    patternProperties:
> > +      '-pins$':
> > +        type: object
> > +        $ref: /schemas/pinctrl/pincfg-node.yaml#
> > +        additionalProperties: false
> > +
> > +        properties:
> > +          pins:
> > +            enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
> > +
> > +          function:
> > +            enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
> > +                    SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
> > +                    GPI, GPOH, GPOL ]
> > +
> > +        required:
> > +          - pins
> > +          - function
> > +
> > +  lantiq,data-rate-bps:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [2048000, 4096000, 8192000, 16384000]
> > +    default: 2048000
> > +    description:
> > +      Data rate (bit per seconds) on the system highway.
> > +
> > +  lantiq,clock-falling-edge:
> > +    $ref: /schemas/types.yaml#/definitions/flag
> > +    description:
> > +      Data is sent on falling edge of the clock (and received on the rising
> > +      edge). If 'clock-falling-edge' is not present, data is sent on the
> > +      rising edge (and received on the falling edge).
> > +
> > +  lantiq,channel-phase:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2, 3, 4, 5, 6, 7]
> > +    default: 0
> > +    description:
> > +      The pef2256 delivers a full frame (32 8bit time-slots in E1 and 24 8bit
> > +      time-slots 8 8bit signaling in E1/J1) every 125us. This lead to a data
> > +      rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
> > +      bit/s, the data (all 32 8bit) present in the frame are interleave with
> > +      unused time-slots. The lantiq,channel-phase property allows to set the
> > +      correct alignment of the interleave mechanism.
> > +      For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
> > +      lantiq,channel-phase = 2, the interleave schema with unused time-slots
> > +      (nu) and used time-slots (XX) for TSi is
> > +        nu nu XX nu nu nu XX nu nu nu XX nu
> > +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> > +      With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
> > +      interleave schema is
> > +        nu XX nu nu nu XX nu nu nu XX nu nu
> > +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> > +      With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
> > +      lantiq,channel-phase = 1, the interleave schema is
> > +        nu    XX    nu    XX    nu    XX
> > +        <-- TSi --> <- TSi+1 -> <- TSi+2 ->
> > +
> > +patternProperties:
> > +  '^codec(-([0-9]|[1-2][0-9]|3[0-1]))?$':
> > +    type: object
> > +    $ref: /schemas/sound/dai-common.yaml
> > +    unevaluatedProperties: false
> > +    description:
> > +      Codec provided by the pef2256. This codec allows to use some of the PCM
> > +      system highway time-slots as audio channels to transport audio data over
> > +      the E1/T1/J1 lines.
> > +      The time-slots used by the codec must be set and so, the properties
> > +      'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
> > +      'dai-tdm-slot-rx-mask' must be present in the sound card node for
> > +      sub-nodes that involve the codec. The codec uses 8bit time-slots.
> > +      'dai-tdm-tdm-slot-with' must be set to 8.
> > +      The tx and rx masks define the pef2256 time-slots assigned to the codec.
> > +
> > +    properties:
> > +      compatible:
> > +        const: lantiq,pef2256-codec
> > +
> > +      '#sound-dai-cells':
> > +        const: 0
> > +
> > +      framer:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description:
> > +          phandle to the framer node  
> 
> That's just the parent. Why do you need this?

It is a mistake.
You're right, as it simply refers the parent it is not needed.
This 'framer' phandle will be removed in the next iteration.

Regards,
Hervé

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Re: [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer

[Andrew Lunn]

> +static inline u8 pef2256_read8(struct pef2256 *pef2256, int offset)
> +{
> +	int val;
> +
> +	regmap_read(pef2256->regmap, offset, &val);
> +	return val;
> +}
> +
> +static inline void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)
> +{
> +	regmap_write(pef2256->regmap, offset, val);
> +}

More cases of inline functions in .C files. Please let the compiler
decide.

> +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> +{
> +	dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
> +}

Should this be rate limited? It is going to be very noise if it gets
called once per frame time.

       Andrew

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Re: [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer

[Herve Codina]

On Tue, 1 Aug 2023 12:22:39 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > +static inline u8 pef2256_read8(struct pef2256 *pef2256, int offset)
> > +{
> > +	int val;
> > +
> > +	regmap_read(pef2256->regmap, offset, &val);
> > +	return val;
> > +}
> > +
> > +static inline void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)
> > +{
> > +	regmap_write(pef2256->regmap, offset, val);
> > +}  
> 
> More cases of inline functions in .C files. Please let the compiler
> decide.

Will be changed.

> 
> > +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> > +{
> > +	dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
> > +}  
> 
> Should this be rate limited? It is going to be very noise if it gets
> called once per frame time.

This function should not be called.
It is wired on some interrupts and these interrupts should not be triggered.
It they fired, something was wrong.

I would prefer to keep this dev_warn() to keep the user informed about the
problem.

Regards,
Hervé


-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer

[Andrew Lunn]

> > > +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> > > +{
> > > +	dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
> > > +}  
> > 
> > Should this be rate limited? It is going to be very noise if it gets
> > called once per frame time.
> 
> This function should not be called.
> It is wired on some interrupts and these interrupts should not be triggered.
> It they fired, something was wrong.
> 
> I would prefer to keep this dev_warn() to keep the user informed about the
> problem.

I would definitely keep it, but rate limit it. dev_warn_ratelimited().

	Andrew

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Re: [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer

[Herve Codina]

On Tue, 1 Aug 2023 12:52:29 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > > > +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> > > > +{
> > > > +	dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
> > > > +}    
> > > 
> > > Should this be rate limited? It is going to be very noise if it gets
> > > called once per frame time.  
> > 
> > This function should not be called.
> > It is wired on some interrupts and these interrupts should not be triggered.
> > It they fired, something was wrong.
> > 
> > I would prefer to keep this dev_warn() to keep the user informed about the
> > problem.  
> 
> I would definitely keep it, but rate limit it. dev_warn_ratelimited().
> 
> 	Andrew

Ok, will be changed to dev_warn_ratelimited().

Hervé

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Re: [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/net/wan/framer/Kconfig                |  16 +
>   drivers/net/wan/framer/Makefile               |   1 +
>   drivers/net/wan/framer/pef2256/Makefile       |   8 +
>   drivers/net/wan/framer/pef2256/pef2256-regs.h | 250 +++++
>   drivers/net/wan/framer/pef2256/pef2256.c      | 880 ++++++++++++++++++
>   include/linux/framer/pef2256.h                |  31 +
>   6 files changed, 1186 insertions(+)
>   create mode 100644 drivers/net/wan/framer/pef2256/Makefile
>   create mode 100644 drivers/net/wan/framer/pef2256/pef2256-regs.h
>   create mode 100644 drivers/net/wan/framer/pef2256/pef2256.c
>   create mode 100644 include/linux/framer/pef2256.h
> 
> diff --git a/drivers/net/wan/framer/Kconfig b/drivers/net/wan/framer/Kconfig
> index 96ef1e7ba8eb..ba43d7f162a2 100644
> --- a/drivers/net/wan/framer/Kconfig
> +++ b/drivers/net/wan/framer/Kconfig
> @@ -16,4 +16,20 @@ config GENERIC_FRAMER
>   	  framework and framer users can obtain reference to the framer.
>   	  All the users of this framework should select this config.
>   
> +config FRAMER_PEF2256
> +	tristate "Lantiq PEF2256"
> +	depends on OF
> +	select GENERIC_FRAMER
> +	select MFD_CORE
> +	select REGMAP_MMIO
> +	help
> +	  Enable support for the Lantiq PEF2256 (FALC56) framer.
> +	  The PEF2256 is a framer and line interface between analog E1/T1/J1
> +	  line and a digital PCM bus.
> +
> +	  If unsure, say N.
> +
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called framer-pef2256.
> +
>   endmenu
> diff --git a/drivers/net/wan/framer/Makefile b/drivers/net/wan/framer/Makefile
> index 78dbd8e563d0..3403f2b14534 100644
> --- a/drivers/net/wan/framer/Makefile
> +++ b/drivers/net/wan/framer/Makefile
> @@ -4,3 +4,4 @@
>   #
>   
>   obj-$(CONFIG_GENERIC_FRAMER)			+= framer-core.o
> +obj-$(CONFIG_FRAMER_PEF2256)			+= pef2256/
> diff --git a/drivers/net/wan/framer/pef2256/Makefile b/drivers/net/wan/framer/pef2256/Makefile
> new file mode 100644
> index 000000000000..f4d1208dd8a4
> --- /dev/null
> +++ b/drivers/net/wan/framer/pef2256/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for the pef2256 driver.
> +#
> +
> +obj-$(CONFIG_FRAMER_PEF2256)		+= framer-pef2256.o
> +
> +framer-pef2256-objs	:= pef2256.o
> diff --git a/drivers/net/wan/framer/pef2256/pef2256-regs.h b/drivers/net/wan/framer/pef2256/pef2256-regs.h
> new file mode 100644
> index 000000000000..5d3183c91714
> --- /dev/null
> +++ b/drivers/net/wan/framer/pef2256/pef2256-regs.h
> @@ -0,0 +1,250 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * PEF2256 registers definition
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +#ifndef __PEF2256_REGS_H__
> +#define __PEF2256_REGS_H__
> +
> +#include "linux/bitfield.h"
> +
> +/* Command Register */
> +#define PEF2256_CMDR		0x02
> +#define PEF2256_CMDR_RRES	BIT(6)
> +#define PEF2256_CMDR_XRES	BIT(4)
> +#define PEF2256_CMDR_SRES	BIT(0)
> +
> +/* Interrupt Mask Register 0..5 */
> +#define PEF2256_IMR0	        0x14
> +#define PEF2256_IMR1	        0x15
> +#define PEF2256_IMR2	        0x16
> +#define PEF2256_IMR3	        0x17
> +#define PEF2256_IMR4	        0x18
> +#define PEF2256_IMR5	        0x19
> +
> +/* Framer Mode Register 0 */
> +#define PEF2256_FMR0		0x1C
> +#define PEF2256_FMR0_XC_MASK	GENMASK(7, 6)
> +#define PEF2256_FMR0_XC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
> +#define PEF2256_FMR0_XC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
> +#define PEF2256_FMR0_XC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
> +#define PEF2256_FMR0_XC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
> +#define PEF2256_FMR0_RC_MASK	GENMASK(5, 4)
> +#define PEF2256_FMR0_RC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
> +#define PEF2256_FMR0_RC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
> +#define PEF2256_FMR0_RC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
> +#define PEF2256_FMR0_RC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
> +
> +/* Framer Mode Register 1 */
> +#define PEF2256_FMR1		0x1D
> +#define PEF2256_FMR1_XFS	BIT(3)
> +#define PEF2256_FMR1_ECM	BIT(2)
> +/* SSD is defined on 2 bits. The other bit is on SIC1 register */
> +#define PEF2256_FMR1_SSD_MASK	GENMASK(1, 1)
> +#define PEF2256_FMR1_SSD_2048	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
> +#define PEF2256_FMR1_SSD_4096	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
> +#define PEF2256_FMR1_SSD_8192	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
> +#define PEF2256_FMR1_SSD_16384	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
> +
> +/* Framer Mode Register 2 */
> +#define PEF2256_FMR2			  0x1E
> +#define PEF2256_FMR2_RFS_MASK		  GENMASK(7, 6)
> +#define PEF2256_FMR2_RFS_DOUBLEFRAME	  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0)
> +#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2)
> +#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)
> +#define PEF2256_FMR2_AXRA		  BIT(1)
> +
> +/* Transmit Service Word */
> +#define PEF2256_XSW		0x20
> +#define PEF2256_XSW_XSIS	BIT(7)
> +#define PEF2256_XSW_XTM		BIT(6)
> +#define PEF2256_XSW_XY_MASK	GENMASK(5, 0)
> +#define PEF2256_XSW_XY(_v)	FIELD_PREP(PEF2256_XSW_XY_MASK, _v)
> +
> +/* Transmit Spare Bits */
> +#define PEF2256_XSP	        0x21
> +#define PEF2256_XSP_XSIF	BIT(2)
> +
> +/* Transmit Control 0..1 */
> +#define PEF2256_XC0		0x22
> +#define PEF2256_XC1		0x23
> +
> +/* Receive Control 0 */
> +#define PEF2256_RC0		0x24
> +#define PEF2256_RC0_SWD		BIT(7)
> +#define PEF2256_RC0_ASY4	BIT(6)
> +
> +/* Receive Control 1 */
> +#define PEF2256_RC1		0x25
> +
> +/* Transmit Pulse Mask 0..1 */
> +#define PEF2256_XPM0		0x26
> +#define PEF2256_XPM1		0x27
> +
> +/* Transmit Pulse Mask 2 */
> +#define PEF2256_XPM2		0x28
> +#define PEF2256_XPM2_XLT	BIT(6)
> +
> +/* Transparent Service Word Mask */
> +#define PEF2256_TSWM		0x29
> +
> +/* Line Interface Mode 0 */
> +#define PEF2256_LIM0		0x36
> +#define PEF2256_2X_LIM0_BIT3	BIT(3) /* v2.x, described as a forced '1' bit */
> +#define PEF2256_LIM0_MAS	BIT(0)
> +
> +/* Line Interface Mode 1 */
> +#define PEF2256_LIM1		  0x37
> +#define PEF2256_12_LIM1_RIL_MASK  GENMASK(6, 4)
> +#define PEF2256_12_LIM1_RIL_910	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x0)
> +#define PEF2256_12_LIM1_RIL_740	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x1)
> +#define PEF2256_12_LIM1_RIL_590	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x2)
> +#define PEF2256_12_LIM1_RIL_420	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3)
> +#define PEF2256_12_LIM1_RIL_320	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x4)
> +#define PEF2256_12_LIM1_RIL_210	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x5)
> +#define PEF2256_12_LIM1_RIL_160	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x6)
> +#define PEF2256_12_LIM1_RIL_100	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x7)
> +#define PEF2256_2X_LIM1_RIL_MASK  GENMASK(6, 4)
> +#define PEF2256_2X_LIM1_RIL_2250  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x0)
> +#define PEF2256_2X_LIM1_RIL_1100  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x1)
> +#define PEF2256_2X_LIM1_RIL_600	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x2)
> +#define PEF2256_2X_LIM1_RIL_350	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3)
> +#define PEF2256_2X_LIM1_RIL_210	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x4)
> +#define PEF2256_2X_LIM1_RIL_140	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x5)
> +#define PEF2256_2X_LIM1_RIL_100	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x6)
> +#define PEF2256_2X_LIM1_RIL_50	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x7)
> +
> +/* Pulse Count Detection */
> +#define PEF2256_PCD		0x38
> +
> + /* Pulse Count Recovery */
> +#define PEF2256_PCR		0x39
> +
> + /* Line Interface Mode 2 */
> +#define PEF2256_LIM2		0x3A
> +#define PEF2256_LIM2_SLT_MASK	GENMASK(5, 4)
> +#define PEF2256_LIM2_SLT_THR55	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x0)
> +#define PEF2256_LIM2_SLT_THR67	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x1)
> +#define PEF2256_LIM2_SLT_THR50	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x2)
> +#define PEF2256_LIM2_SLT_THR45	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3)
> +#define PEF2256_LIM2_ELT	BIT(2)
> +
> +/* System Interface Control 1 */
> +#define PEF2256_SIC1	          0x3E
> +#define PEF2256_SIC1_SSC_MASK	  (BIT(7) |  BIT(3))
> +#define PEF2256_SIC1_SSC_2048	  (0)
> +#define PEF2256_SIC1_SSC_4096	  BIT(3)
> +#define PEF2256_SIC1_SSC_8192	  BIT(7)
> +#define PEF2256_SIC1_SSC_16384	  (BIT(7) |  BIT(3))
> +/* SSD is defined on 2 bits. The other bit is on FMR1 register */
> +#define PEF2256_SIC1_SSD_MASK	  GENMASK(6, 6)
> +#define PEF2256_SIC1_SSD_2048	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
> +#define PEF2256_SIC1_SSD_4096	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
> +#define PEF2256_SIC1_SSD_8192	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
> +#define PEF2256_SIC1_SSD_16384	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
> +#define PEF2256_SIC1_RBS_MASK	  GENMASK(5, 4)
> +#define PEF2256_SIC1_RBS_2FRAMES  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x0)
> +#define PEF2256_SIC1_RBS_1FRAME	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x1)
> +#define PEF2256_SIC1_RBS_96BITS	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x2)
> +#define PEF2256_SIC1_RBS_BYPASS	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3)
> +#define PEF2256_SIC1_XBS_MASK	  GENMASK(1, 0)
> +#define PEF2256_SIC1_XBS_BYPASS	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x0)
> +#define PEF2256_SIC1_XBS_1FRAME	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x1)
> +#define PEF2256_SIC1_XBS_2FRAMES  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x2)
> +#define PEF2256_SIC1_XBS_96BITS	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3)
> +
> +/* System Interface Control 2 */
> +#define PEF2256_SIC2		0x3F
> +#define PEF2256_SIC2_SICS_MASK	GENMASK(3, 1)
> +#define PEF2256_SIC2_SICS(_v)	FIELD_PREP(PEF2256_SIC2_SICS_MASK, _v)
> +
> +/* System Interface Control 3 */
> +#define PEF2256_SIC3		0x40
> +#define PEF2256_SIC3_RTRI	BIT(5)
> +#define PEF2256_SIC3_RESX	BIT(3)
> +#define PEF2256_SIC3_RESR	BIT(2)
> +
> +/* Clock Mode Register 1 */
> +#define PEF2256_CMR1			0x44
> +#define PEF2256_CMR1_RS_MASK		GENMASK(5, 4)
> +#define PEF2256_CMR1_RS_DPLL		FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x0)
> +#define PEF2256_CMR1_RS_DPLL_LOS_HIGH	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x1)
> +#define PEF2256_CMR1_RS_DCOR_2048	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x2)
> +#define PEF2256_CMR1_RS_DCOR_8192	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3)
> +#define PEF2256_CMR1_DCS		BIT(3)
> +
> +/* Clock Mode Register 2 */
> +#define PEF2256_CMR2		0x45
> +#define PEF2256_CMR2_DCOXC	BIT(5)
> +
> +/* Global Configuration Register */
> +#define PEF2256_GCR		0x46
> +#define PEF2256_GCR_SCI		BIT(6)
> +#define PEF2256_GCR_ECMC	BIT(4)
> +
> +/* Port Configuration 5 */
> +#define PEF2256_PC5		0x84
> +#define PEF2256_PC5_CRP         BIT(0)
> +
> +/* Global Port Configuration 1 */
> +#define PEF2256_GPC1			0x85
> +#define PEF2256_GPC1_CSFP_MASK		GENMASK(7, 5)
> +#define PEF2256_GPC1_CSFP_SEC_IN_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x0)
> +#define PEF2256_GPC1_CSFP_SEC_OUT_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x1)
> +#define PEF2256_GPC1_CSFP_FSC_OUT_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x2)
> +#define PEF2256_GPC1_CSFP_FSC_OUT_LOW	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3)
> +
> +/* Port Configuration 6 */
> +#define PEF2256_PC6		0x86
> +
> +/* Global Counter Mode n=1..8 */
> +#define PEF2256_GCM(_n)         (0x92 + (_n) - 1)
> +#define PEF2256_GCM1	        0x92
> +#define PEF2256_GCM2	        0x93
> +#define PEF2256_GCM3	        0x94
> +#define PEF2256_GCM4	        0x95
> +#define PEF2256_GCM5	        0x96
> +#define PEF2256_GCM6	        0x97
> +#define PEF2256_GCM7	        0x98
> +#define PEF2256_GCM8	        0x99
> +
> +/* Version Status Register */
> +#define PEF2256_VSTR		 0x4A
> +#define PEF2256_VSTR_VERSION_12	 0x00
> +#define PEF2256_VSTR_VERSION_21	 0x10
> +#define PEF2256_VSTR_VERSION_2x	 0x05
> +
> +/* Framer Receive Status 0 */
> +#define PEF2256_FRS0		0x4C
> +#define PEF2256_FRS0_LOS	BIT(7)
> +#define PEF2256_FRS0_AIS	BIT(6)
> +
> +/* Interrupt Status Register 0..5 */
> +#define PEF2256_ISR(_n)		(0x68 + (_n))
> +#define PEF2256_ISR0		0x68
> +#define PEF2256_ISR1		0x69
> +#define PEF2256_ISR2		0x6A
> +#define PEF2256_ISR3		0x6B
> +#define PEF2256_ISR4		0x6C
> +#define PEF2256_ISR5		0x6D
> +
> +/* Global Interrupt Status */
> +#define PEF2256_GIS		0x6E
> +#define PEF2256_GIS_ISR(_n)	BIT(_n)
> +
> +/* Wafer Identification Register */
> +#define PEF2256_WID		   0xEC
> +#define PEF2256_12_WID_MASK	   GENMASK(1, 0)
> +#define PEF2256_12_WID_VERSION_12  FIELD_PREP_CONST(PEF2256_12_WID_MASK, 0x3)
> +#define PEF2256_2X_WID_MASK	   GENMASK(7, 6)
> +#define PEF2256_2X_WID_VERSION_21  FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x0)
> +#define PEF2256_2X_WID_VERSION_22  FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x1)
> +
> +/* IMR2/ISR2 Interrupts common bits */
> +#define PEF2256_INT2_AIS	BIT(3)
> +#define PEF2256_INT2_LOS	BIT(2)
> +
> +#endif /* __PEF2256_REGS_H__ */
> diff --git a/drivers/net/wan/framer/pef2256/pef2256.c b/drivers/net/wan/framer/pef2256/pef2256.c
> new file mode 100644
> index 000000000000..1eb5bc404278
> --- /dev/null
> +++ b/drivers/net/wan/framer/pef2256/pef2256.c
> @@ -0,0 +1,880 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PEF2256 also known as FALC56 driver
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#include <linux/framer/pef2256.h>
> +#include <linux/clk.h>
> +#include <linux/framer/framer-provider.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include "pef2256-regs.h"
> +
> +enum pef2256_frame_type {
> +	PEF2256_FRAME_E1_DOUBLEFRAME,
> +	PEF2256_FRAME_E1_CRC4_MULTIFRAME,
> +	PEF2256_FRAME_E1_AUTO_MULTIFRAME,
> +	PEF2256_FRAME_T1J1_4FRAME,
> +	PEF2256_FRAME_T1J1_12FRAME,
> +	PEF2256_FRAME_T1J1_24FRAME,
> +	PEF2256_FRAME_T1J1_72FRAME,
> +};
> +
> +struct pef2256 {
> +	struct device *dev;
> +	struct regmap *regmap;
> +	enum pef2256_version version;
> +	struct clk *mclk;
> +	struct clk *sclkr;
> +	struct clk *sclkx;
> +	struct gpio_desc *reset_gpio;
> +	unsigned long sysclk_rate;
> +	u32 data_rate;
> +	bool is_tx_falling_edge;
> +	bool is_subordinate;
> +	enum pef2256_frame_type frame_type;
> +	u8 channel_phase;
> +	atomic_t carrier;
> +	struct framer *framer;
> +};
> +
> +static inline u8 pef2256_read8(struct pef2256 *pef2256, int offset)
> +{
> +	int val;
> +
> +	regmap_read(pef2256->regmap, offset, &val);
> +	return val;
> +}
> +
> +static inline void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)
> +{
> +	regmap_write(pef2256->regmap, offset, val);
> +}
> +
> +static inline void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr)
> +{
> +	regmap_clear_bits(pef2256->regmap, offset, clr);
> +}
> +
> +static inline void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set)
> +{
> +	regmap_set_bits(pef2256->regmap, offset, set);
> +}
> +
> +static inline void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set)
> +{
> +	regmap_update_bits(pef2256->regmap, offset, clr | set, set);
> +}
> +
> +enum pef2256_version pef2256_get_version(struct pef2256 *pef2256)
> +{
> +	enum pef2256_version version = PEF2256_VERSION_UNKNOWN;
> +	u8 vstr, wid;
> +
> +	vstr = pef2256_read8(pef2256, PEF2256_VSTR);
> +	wid = pef2256_read8(pef2256, PEF2256_WID);
> +
> +	switch (vstr) {
> +	case PEF2256_VSTR_VERSION_12:
> +		if ((wid & PEF2256_12_WID_MASK) == PEF2256_12_WID_VERSION_12)
> +			version = PEF2256_VERSION_1_2;
> +		break;
> +	case PEF2256_VSTR_VERSION_2x:
> +		switch (wid & PEF2256_2X_WID_MASK) {
> +		case PEF2256_2X_WID_VERSION_21:
> +			version = PEF2256_VERSION_2_1;
> +			break;
> +		case PEF2256_2X_WID_VERSION_22:
> +			version = PEF2256_VERSION_2_2;
> +			break;
> +		}
> +		break;
> +	case PEF2256_VSTR_VERSION_21:
> +		version = PEF2256_VERSION_2_1;
> +		break;
> +	}
> +
> +	if (version == PEF2256_VERSION_UNKNOWN)
> +		dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid);
> +
> +	return version;
> +}
> +EXPORT_SYMBOL_GPL(pef2256_get_version);
> +
> +enum pef2256_gcm_config_item {
> +	PEF2256_GCM_CONFIG_1544000 = 0,
> +	PEF2256_GCM_CONFIG_2048000,
> +	PEF2256_GCM_CONFIG_8192000,
> +	PEF2256_GCM_CONFIG_10000000,
> +	PEF2256_GCM_CONFIG_12352000,
> +	PEF2256_GCM_CONFIG_16384000,
> +};
> +
> +struct pef2256_gcm_config {
> +	u8 gcm_12[6];
> +	u8 gcm_2x[8];
> +};
> +
> +static const struct pef2256_gcm_config pef2256_gcm_configs[] = {
> +	[PEF2256_GCM_CONFIG_1544000] = {
> +		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x00, 0x15},
> +		.gcm_2x = {0x00, 0x15, 0x00, 0x08, 0x00, 0x3F, 0x9C, 0xDF},
> +	},
> +	[PEF2256_GCM_CONFIG_2048000] = {
> +		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x00, 0x10},
> +		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x2F, 0xDB, 0xDF},
> +	},
> +	[PEF2256_GCM_CONFIG_8192000] = {
> +		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x03, 0x10},
> +		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x0B, 0xDB, 0xDF},
> +	},
> +	[PEF2256_GCM_CONFIG_10000000] = {
> +		.gcm_12 = {0x90, 0x51, 0x81, 0x8F, 0x04, 0x10},
> +		.gcm_2x = {0x40, 0x1B, 0x3D, 0x0A, 0x00, 0x07, 0xC9, 0xDC},
> +	},
> +	[PEF2256_GCM_CONFIG_12352000] = {
> +		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x07, 0x15},
> +		.gcm_2x = {0x00, 0x19, 0x00, 0x08, 0x01, 0x0A, 0x98, 0xDA},
> +	},
> +	[PEF2256_GCM_CONFIG_16384000] = {
> +		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x07, 0x10},
> +		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x01, 0x0B, 0xDB, 0xDF},
> +	},
> +};
> +
> +static int pef2256_setup_gcm(struct pef2256 *pef2256)
> +{
> +	enum pef2256_gcm_config_item item;
> +	unsigned long mclk_rate;
> +	const u8 *gcm;
> +	int i, count;
> +
> +	mclk_rate = clk_get_rate(pef2256->mclk);
> +	switch (mclk_rate) {
> +	case 1544000:
> +		item = PEF2256_GCM_CONFIG_1544000;
> +		break;
> +	case 2048000:
> +		item = PEF2256_GCM_CONFIG_2048000;
> +		break;
> +	case 8192000:
> +		item = PEF2256_GCM_CONFIG_8192000;
> +		break;
> +	case 10000000:
> +		item = PEF2256_GCM_CONFIG_10000000;
> +		break;
> +	case 12352000:
> +		item = PEF2256_GCM_CONFIG_12352000;
> +		break;
> +	case 16384000:
> +		item = PEF2256_GCM_CONFIG_16384000;
> +		break;
> +	default:
> +		dev_err(pef2256->dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate);
> +		return -EINVAL;
> +	}
> +
> +	BUILD_BUG_ON(item >= ARRAY_SIZE(pef2256_gcm_configs));
> +
> +	if (pef2256->version == PEF2256_VERSION_1_2) {
> +		gcm = pef2256_gcm_configs[item].gcm_12;
> +		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_12);
> +	} else {
> +		gcm = pef2256_gcm_configs[item].gcm_2x;
> +		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_2x);
> +	}
> +
> +	for (i = 0; i < count; i++)
> +		pef2256_write8(pef2256, PEF2256_GCM(i + 1), *(gcm + i));
> +
> +	return 0;
> +}
> +
> +static int pef2256_setup_e1_line(struct pef2256 *pef2256)
> +{
> +	u8 fmr1, fmr2;
> +
> +	/* RCLK output : DPLL clock, DCO-X enabled, DCO-X internal ref clock */
> +	pef2256_write8(pef2256, PEF2256_CMR1, 0x00);
> +
> +	/* SCLKR selected, SCLKX selected,
> +	 * receive synchro pulse sourced by SYPR,
> +	 * transmit synchro pulse sourced by SYPX,
> +	 * DCO-X center frequency enabled
> +	 */
> +	pef2256_write8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC);
> +
> +	if (pef2256->is_subordinate) {
> +		/* select RCLK source = 2M,  disable switching from RCLK to SYNC */
> +		pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK,
> +				    PEF2256_CMR1_RS_DCOR_2048 | PEF2256_CMR1_DCS);
> +	}
> +
> +	/* slave mode, local loop off, mode short-haul
> +	 * In v2.x, bit3 is a forced 1 bit in the datasheet -> Need to be set.
> +	 */
> +	if (pef2256->version == PEF2256_VERSION_1_2)
> +		pef2256_write8(pef2256, PEF2256_LIM0, 0x00);
> +	else
> +		pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3);
> +
> +	/* "master" mode */
> +	if (!pef2256->is_subordinate)
> +		pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS);
> +
> +	/* analog interface selected, remote loop off */
> +	pef2256_write8(pef2256, PEF2256_LIM1, 0x00);
> +
> +	/* receive input threshold = 0,21V */
> +	if (pef2256->version == PEF2256_VERSION_1_2)
> +		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK,
> +				    PEF2256_12_LIM1_RIL_210);
> +	else
> +		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK,
> +				    PEF2256_2X_LIM1_RIL_210);
> +
> +	/* transmit pulse mask, default value from datasheet
> +	 * transmit line in normal operation
> +	 */
> +	if (pef2256->version == PEF2256_VERSION_1_2)
> +		pef2256_write8(pef2256, PEF2256_XPM0, 0x7B);
> +	else
> +		pef2256_write8(pef2256, PEF2256_XPM0, 0x9C);
> +	pef2256_write8(pef2256, PEF2256_XPM1, 0x03);
> +	pef2256_write8(pef2256, PEF2256_XPM2, 0x00);
> +
> +	/* HDB3 coding, no alarm simulation */
> +	pef2256_write8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_HDB3 | PEF2256_FMR0_RC_HDB3);
> +
> +	/* E1, frame format, 2 Mbit/s system data rate, no AIS
> +	 * transmission to remote end or system interface, payload loop
> +	 * off, transmit remote alarm on
> +	 */
> +	fmr1 = 0x00;
> +	fmr2 = PEF2256_FMR2_AXRA;
> +	switch (pef2256->frame_type) {
> +	case PEF2256_FRAME_E1_DOUBLEFRAME:
> +		fmr2 |= PEF2256_FMR2_RFS_DOUBLEFRAME;
> +		break;
> +	case PEF2256_FRAME_E1_CRC4_MULTIFRAME:
> +		fmr1 |= PEF2256_FMR1_XFS;
> +		fmr2 |= PEF2256_FMR2_RFS_CRC4_MULTIFRAME;
> +		break;
> +	case PEF2256_FRAME_E1_AUTO_MULTIFRAME:
> +		fmr1 |= PEF2256_FMR1_XFS;
> +		fmr2 |= PEF2256_FMR2_RFS_AUTO_MULTIFRAME;
> +		break;
> +	default:
> +		dev_err(pef2256->dev, "Unsupported frame type %d\n", pef2256->frame_type);
> +		return -EINVAL;
> +	}
> +	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_XFS, fmr1);
> +	pef2256_write8(pef2256, PEF2256_FMR2, fmr2);
> +
> +	if (!pef2256->is_subordinate) {
> +		/* SEC input, active high */
> +		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH);
> +	} else {
> +		/* FSC output, active high */
> +		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH);
> +	}
> +
> +	/* SCLKR, SCLKX, RCLK configured to inputs,
> +	 * XFMS active low, CLK1 and CLK2 pin configuration
> +	 */
> +	pef2256_write8(pef2256, PEF2256_PC5, 0x00);
> +	pef2256_write8(pef2256, PEF2256_PC6, 0x00);
> +
> +	/* port RCLK is output */
> +	pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP);
> +
> +	return 0;
> +}
> +
> +static void pef2256_setup_e1_los(struct pef2256 *pef2256)
> +{
> +	/* detection of LOS alarm = 176 pulses (ie (10 + 1) * 16) */
> +	pef2256_write8(pef2256, PEF2256_PCD, 10);
> +	/* recovery of LOS alarm = 22 pulses (ie 21 + 1) */
> +	pef2256_write8(pef2256, PEF2256_PCR, 21);
> +	/* E1 default for the receive slicer threshold */
> +	pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50);
> +	if (pef2256->is_subordinate) {
> +		/* Loop-timed */
> +		pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT);
> +	}
> +}
> +
> +static int pef2256_setup_e1_system(struct pef2256 *pef2256)
> +{
> +	u8 sic1, fmr1;
> +
> +	/* 2.048 MHz system clocking rate, receive buffer 2 frames, transmit
> +	 * buffer bypass, data sampled and transmitted on the falling edge of
> +	 * SCLKR/X, automatic freeze signaling, data is active in the first
> +	 * channel phase
> +	 */
> +	pef2256_write8(pef2256, PEF2256_SIC1, 0x00);
> +	pef2256_write8(pef2256, PEF2256_SIC2, 0x00);
> +	pef2256_write8(pef2256, PEF2256_SIC3, 0x00);
> +
> +	if (pef2256->is_subordinate) {
> +		/* transmit buffer size = 2 frames, transparent mode */
> +		pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK,
> +				    PEF2256_SIC1_XBS_2FRAMES);
> +	}
> +
> +	if (pef2256->version != PEF2256_VERSION_1_2) {
> +		/* during inactive channel phase switch RDO/RSIG into tri-state */
> +		pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI);
> +	}
> +
> +	if (pef2256->is_tx_falling_edge) {
> +		/* falling edge sync pulse transmit, rising edge sync pulse receive */
> +		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESX, PEF2256_SIC3_RESR);
> +	} else {
> +		/* rising edge sync pulse transmit, falling edge sync pulse receive */
> +		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESR, PEF2256_SIC3_RESX);
> +	}
> +
> +	/* transmit offset counter (XCO10..0) = 4 */
> +	pef2256_write8(pef2256, PEF2256_XC0, 0);
> +	pef2256_write8(pef2256, PEF2256_XC1, 4);
> +	/* receive offset counter (RCO10..0) = 4 */
> +	pef2256_write8(pef2256, PEF2256_RC0, 0);
> +	pef2256_write8(pef2256, PEF2256_RC1, 4);
> +
> +	/* system clock rate */
> +	switch (pef2256->sysclk_rate) {
> +	case 2048000:
> +		sic1 = PEF2256_SIC1_SSC_2048;
> +		break;
> +	case 4096000:
> +		sic1 = PEF2256_SIC1_SSC_4096;
> +		break;
> +	case 8192000:
> +		sic1 = PEF2256_SIC1_SSC_8192;
> +		break;
> +	case 16384000:
> +		sic1 = PEF2256_SIC1_SSC_16384;
> +		break;
> +	default:
> +		dev_err(pef2256->dev, "Unsupported sysclk rate %lu\n", pef2256->sysclk_rate);
> +		return -EINVAL;
> +	}
> +	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1);
> +
> +	/* data clock rate */
> +	switch (pef2256->data_rate) {
> +	case 2048000:
> +		fmr1 = PEF2256_FMR1_SSD_2048;
> +		sic1 = PEF2256_SIC1_SSD_2048;
> +		break;
> +	case 4096000:
> +		fmr1 = PEF2256_FMR1_SSD_4096;
> +		sic1 = PEF2256_SIC1_SSD_4096;
> +		break;
> +	case 8192000:
> +		fmr1 = PEF2256_FMR1_SSD_8192;
> +		sic1 = PEF2256_SIC1_SSD_8192;
> +		break;
> +	case 16384000:
> +		fmr1 = PEF2256_FMR1_SSD_16384;
> +		sic1 = PEF2256_SIC1_SSD_16384;
> +		break;
> +	default:
> +		dev_err(pef2256->dev, "Unsupported data rate %u\n", pef2256->data_rate);
> +		return -EINVAL;
> +	}
> +	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1);
> +	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1);
> +
> +	/* channel phase */
> +	pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK,
> +			    PEF2256_SIC2_SICS(pef2256->channel_phase));
> +
> +	return 0;
> +}
> +
> +static void pef2256_setup_e1_signaling(struct pef2256 *pef2256)
> +{
> +	/* All bits of the transmitted service word are cleared */
> +	pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F));
> +
> +	/* CAS disabled and clear spare bit values */
> +	pef2256_write8(pef2256, PEF2256_XSP, 0x00);
> +
> +	if (pef2256->is_subordinate) {
> +		/* transparent mode */
> +		pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM);
> +	}
> +
> +	/* Si-Bit, Spare bit For International, FAS word */
> +	pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS);
> +	pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF);
> +
> +	/* no transparent mode active */
> +	pef2256_write8(pef2256, PEF2256_TSWM, 0x00);
> +}
> +
> +static void pef2256_setup_e1_errors(struct pef2256 *pef2256)
> +{
> +	/* error counter latched every 1s */
> +	pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM);
> +
> +	/* error counter mode COFA */
> +	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC);
> +
> +	/* errors in service words have no influence */
> +	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD);
> +
> +	/* 4 consecutive incorrect FAS causes loss of sync */
> +	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4);
> +}
> +
> +static int pef2256_setup_e1(struct pef2256 *pef2256)
> +{
> +	int ret;
> +
> +	/* Setup, Master clocking mode (GCM8..1) */
> +	ret = pef2256_setup_gcm(pef2256);
> +	if (ret)
> +		return ret;
> +
> +	/* Select E1 mode */
> +	pef2256_write8(pef2256, PEF2256_FMR1, 0x00);
> +
> +	/* internal second timer, power on */
> +	pef2256_write8(pef2256, PEF2256_GCR, 0x00);
> +
> +	/* Setup line interface */
> +	ret = pef2256_setup_e1_line(pef2256);
> +	if (ret)
> +		return ret;
> +
> +	/* Setup Loss-of-signal detection and recovery */
> +	pef2256_setup_e1_los(pef2256);
> +
> +	/* Setup system interface */
> +	ret = pef2256_setup_e1_system(pef2256);
> +	if (ret)
> +		return ret;
> +
> +	/* Setup signaling */
> +	pef2256_setup_e1_signaling(pef2256);
> +
> +	/* Setup errors counters and condition */
> +	pef2256_setup_e1_errors(pef2256);
> +
> +	/* status changed interrupt at both up and down */
> +	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI);
> +
> +	/* Clear any ISR2 pending interrupts and unmask needed interrupts */
> +	pef2256_read8(pef2256, PEF2256_ISR2);
> +	pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS);
> +
> +	/* reset lines */
> +	pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES);
> +	return 0;
> +}
> +
> +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> +{
> +	dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
> +}
> +
> +static bool pef2256_is_carrier_on(struct pef2256 *pef2256)
> +{
> +	u8 frs0;
> +
> +	frs0 = pef2256_read8(pef2256, PEF2256_FRS0);
> +	return !(frs0 & (PEF2256_FRS0_LOS | PEF2256_FRS0_AIS));
> +}
> +
> +static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
> +{
> +	bool carrier;
> +
> +	if (isr & (PEF2256_INT2_LOS | PEF2256_INT2_AIS)) {
> +		carrier = pef2256_is_carrier_on(pef2256);
> +		if (atomic_xchg(&pef2256->carrier, carrier) != carrier)
> +			framer_notify_status_change(pef2256->framer);
> +	}
> +}
> +
> +static irqreturn_t pef2256_irq_handler(int irq, void *priv)
> +{
> +	static void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = {
> +		[0] = pef2256_isr_default_handler,
> +		[1] = pef2256_isr_default_handler,
> +		[2] = pef2256_isr2_handler,
> +		[3] = pef2256_isr_default_handler,
> +		[4] = pef2256_isr_default_handler,
> +		[5] = pef2256_isr_default_handler
> +	};
> +	struct pef2256 *pef2256 = (struct pef2256 *)priv;
> +	u8 gis;
> +	u8 isr;
> +	u8 n;
> +
> +	gis = pef2256_read8(pef2256, PEF2256_GIS);
> +
> +	for (n = 0; n < ARRAY_SIZE(pef2256_isr_handler); n++) {
> +		if (gis & PEF2256_GIS_ISR(n)) {
> +			isr = pef2256_read8(pef2256, PEF2256_ISR(n));
> +			pef2256_isr_handler[n](pef2256, n, isr);
> +		}
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate,
> +			       unsigned long data_rate)
> +{
> +	unsigned long rate;
> +
> +	switch (sysclk_rate) {
> +	case 2048000:
> +	case 4096000:
> +	case 8192000:
> +	case 16384000:
> +		break;
> +	default:
> +		dev_err(pef2256->dev, "Unsupported system clock rate %lu\n", sysclk_rate);
> +		return -EINVAL;
> +	}
> +
> +	for (rate = data_rate; rate <= data_rate * 4; rate *= 2) {
> +		if (rate == sysclk_rate)
> +			return 0;
> +	}
> +	dev_err(pef2256->dev, "Unsupported data rate %lu with system clock rate %lu\n",
> +		data_rate, sysclk_rate);
> +	return -EINVAL;
> +}
> +
> +static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np)
> +{
> +	int ret;
> +
> +	pef2256->data_rate = 2048000;
> +	ret = of_property_read_u32(np, "lantiq,data-rate-bps", &pef2256->data_rate);
> +	if (ret && ret != -EINVAL) {
> +		dev_err(pef2256->dev, "%pOF: failed to read lantiq,data-rate-bps\n", np);
> +		return ret;
> +	}
> +
> +	ret =  pef2256_check_rates(pef2256, pef2256->sysclk_rate, pef2256->data_rate);
> +	if (ret)
> +		return ret;
> +
> +	pef2256->is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge");
> +
> +	pef2256->channel_phase = 0;
> +	ret = of_property_read_u8(np, "lantiq,channel-phase", &pef2256->channel_phase);
> +	if (ret && ret != -EINVAL) {
> +		dev_err(pef2256->dev, "%pOF: failed to read lantiq,channel-phase\n",
> +			np);
> +		return ret;
> +	}
> +	if (pef2256->channel_phase >= pef2256->sysclk_rate / pef2256->data_rate) {
> +		dev_err(pef2256->dev, "%pOF: Invalid lantiq,channel-phase %u\n",
> +			np, pef2256->channel_phase);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct regmap_config pef2256_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 8,
> +	.max_register = 0xff,
> +};
> +
> +static const struct mfd_cell pef2256_devs[] = {
> +	{ .name = "lantiq-pef2256-pinctrl", },
> +};
> +
> +static int pef2256_add_audio_devices(struct pef2256 *pef2256)
> +{
> +	const char *compatible = "lantiq,pef2256-codec";
> +	struct mfd_cell *audio_devs;
> +	struct device_node *np;
> +	unsigned int count = 0;
> +	unsigned int i;
> +	int ret;
> +
> +	for_each_available_child_of_node(pef2256->dev->of_node, np) {
> +		if (of_device_is_compatible(np, compatible))
> +			count++;
> +	}
> +
> +	if (!count)
> +		return 0;
> +
> +	audio_devs = kcalloc(count, sizeof(*audio_devs), GFP_KERNEL);
> +	if (!audio_devs)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < count; i++) {
> +		(audio_devs + i)->name = "framer-codec";
> +		(audio_devs + i)->of_compatible = compatible;
> +		(audio_devs + i)->id = i;
> +	}
> +
> +	ret = mfd_add_devices(pef2256->dev, 0, audio_devs, count, NULL, 0, NULL);
> +	kfree(audio_devs);
> +	return ret;
> +}
> +
> +static int pef2256_framer_get_status(struct framer *framer, struct framer_status *status)
> +{
> +	struct pef2256 *pef2256 = framer_get_drvdata(framer);
> +
> +	status->link_is_on = !!atomic_read(&pef2256->carrier);
> +	return 0;
> +}
> +
> +static int pef2256_framer_set_config(struct framer *framer, const struct framer_config *config)
> +{
> +	struct pef2256 *pef2256 = framer_get_drvdata(framer);
> +
> +	if (config->iface != FRAMER_IFACE_E1) {
> +		dev_err(pef2256->dev, "Only E1 line is currently supported\n");
> +		return -EOPNOTSUPP;
> +	}
> +
> +	switch (config->clock_type) {
> +	case FRAMER_CLOCK_EXT:
> +		pef2256->is_subordinate = true;
> +		break;
> +	case FRAMER_CLOCK_INT:
> +		pef2256->is_subordinate = false;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	/* Apply the new settings */
> +	return pef2256_setup_e1(pef2256);
> +}
> +
> +static int pef2256_framer_get_config(struct framer *framer, struct framer_config *config)
> +{
> +	struct pef2256 *pef2256 = framer_get_drvdata(framer);
> +
> +	config->iface = FRAMER_IFACE_E1;
> +	config->clock_type = pef2256->is_subordinate ? FRAMER_CLOCK_EXT : FRAMER_CLOCK_INT;
> +	config->line_clock_rate = 2048000;
> +	return 0;
> +}
> +
> +static const struct framer_ops pef2256_framer_ops = {
> +	.owner = THIS_MODULE,
> +	.get_status = pef2256_framer_get_status,
> +	.get_config = pef2256_framer_get_config,
> +	.set_config = pef2256_framer_set_config,
> +};
> +
> +static int pef2256_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	unsigned long sclkr_rate, sclkx_rate;
> +	struct framer_provider *framer_provider;
> +	struct pef2256 *pef2256;
> +	const char *version_txt;
> +	void __iomem *iomem;
> +	int ret;
> +	int irq;
> +
> +	pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL);
> +	if (!pef2256)
> +		return -ENOMEM;
> +
> +	pef2256->dev = &pdev->dev;
> +	atomic_set(&pef2256->carrier, 0);
> +
> +	pef2256->is_subordinate = true;
> +	pef2256->frame_type = PEF2256_FRAME_E1_DOUBLEFRAME;
> +
> +	iomem = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(iomem))
> +		return PTR_ERR(iomem);
> +
> +	pef2256->regmap = devm_regmap_init_mmio(&pdev->dev, iomem,
> +						&pef2256_regmap_config);
> +	if (IS_ERR(pef2256->regmap)) {
> +		dev_err(&pdev->dev, "Failed to initialise Regmap (%ld)\n",
> +			PTR_ERR(pef2256->regmap));
> +		return PTR_ERR(pef2256->regmap);
> +	}
> +
> +	pef2256->mclk = devm_clk_get_enabled(&pdev->dev, "mclk");
> +	if (IS_ERR(pef2256->mclk))
> +		return PTR_ERR(pef2256->mclk);
> +
> +	pef2256->sclkr = devm_clk_get_enabled(&pdev->dev, "sclkr");
> +	if (IS_ERR(pef2256->sclkr))
> +		return PTR_ERR(pef2256->sclkr);
> +
> +	pef2256->sclkx = devm_clk_get_enabled(&pdev->dev, "sclkx");
> +	if (IS_ERR(pef2256->sclkx))
> +		return PTR_ERR(pef2256->sclkx);
> +
> +	/* Both SCLKR (receive) and SCLKX (transmit) must have the same rate,
> +	 * stored as sysclk_rate.
> +	 * The exact value will be checked at pef2256_check_rates()
> +	 */
> +	sclkr_rate = clk_get_rate(pef2256->sclkr);
> +	sclkx_rate = clk_get_rate(pef2256->sclkx);
> +	if (sclkr_rate != sclkx_rate) {
> +		dev_err(pef2256->dev, "clk rate mismatch. sclkr %lu Hz, sclkx %lu Hz\n",
> +			sclkr_rate, sclkx_rate);
> +		return -EINVAL;
> +	}
> +	pef2256->sysclk_rate = sclkr_rate;
> +
> +	/* Reset the component. The MCLK clock must be active during reset */
> +	pef2256->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
> +	if (IS_ERR(pef2256->reset_gpio))
> +		return PTR_ERR(pef2256->reset_gpio);
> +	if (pef2256->reset_gpio) {
> +		gpiod_set_value_cansleep(pef2256->reset_gpio, 1);
> +		usleep_range(10, 20);
> +		gpiod_set_value_cansleep(pef2256->reset_gpio, 0);
> +		usleep_range(10, 20);
> +	}
> +
> +	pef2256->version = pef2256_get_version(pef2256);
> +	switch (pef2256->version) {
> +	case PEF2256_VERSION_1_2:
> +		version_txt = "1.2";
> +		break;
> +	case PEF2256_VERSION_2_1:
> +		version_txt = "2.1";
> +		break;
> +	case PEF2256_VERSION_2_2:
> +		version_txt = "2.2";
> +		break;
> +	default:
> +		return -ENODEV;
> +	}
> +	dev_info(pef2256->dev, "Version %s detected\n", version_txt);
> +
> +	ret = pef2556_of_parse(pef2256, np);
> +	if (ret)
> +		return ret;
> +
> +	/* Create the framer. It can be used on interrupts */
> +	pef2256->framer = devm_framer_create(pef2256->dev, NULL, &pef2256_framer_ops);
> +	if (IS_ERR(pef2256->framer))
> +		return PTR_ERR(pef2256->framer);
> +
> +	framer_set_drvdata(pef2256->framer, pef2256);
> +
> +	/* Disable interrupts */
> +	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
> +
> +	/* Clear any pending interrupts */
> +	pef2256_read8(pef2256, PEF2256_ISR0);
> +	pef2256_read8(pef2256, PEF2256_ISR1);
> +	pef2256_read8(pef2256, PEF2256_ISR2);
> +	pef2256_read8(pef2256, PEF2256_ISR3);
> +	pef2256_read8(pef2256, PEF2256_ISR4);
> +	pef2256_read8(pef2256, PEF2256_ISR5);
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return irq;
> +	ret = devm_request_irq(pef2256->dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256);
> +	if (ret < 0)
> +		return ret;
> +
> +	platform_set_drvdata(pdev, pef2256);
> +
> +	ret = mfd_add_devices(pef2256->dev, 0, pef2256_devs,
> +			      ARRAY_SIZE(pef2256_devs), NULL, 0, NULL);
> +	if (ret) {
> +		dev_err(pef2256->dev, "add devices failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = pef2256_setup_e1(pef2256);
> +	if (ret)
> +		return ret;
> +
> +	framer_provider = devm_framer_provider_of_register(pef2256->dev,
> +							   framer_provider_simple_of_xlate);
> +	if (IS_ERR(framer_provider))
> +		return PTR_ERR(framer_provider);
> +
> +	/* Add audio devices */
> +	ret = pef2256_add_audio_devices(pef2256);
> +	if (ret < 0) {
> +		dev_err(pef2256->dev, "add audio devices failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int pef2256_remove(struct platform_device *pdev)
> +{
> +	struct pef2256 *pef2256 = platform_get_drvdata(pdev);
> +
> +	/* Disable interrupts */
> +	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
> +	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id pef2256_id_table[] = {
> +	{ .compatible = "lantiq,pef2256" },
> +	{} /* sentinel */
> +};
> +MODULE_DEVICE_TABLE(of, pef2256_id_table);
> +
> +static struct platform_driver pef2256_driver = {
> +	.driver = {
> +		.name = "lantiq-pef2256",
> +		.of_match_table = pef2256_id_table,
> +	},
> +	.probe = pef2256_probe,
> +	.remove = pef2256_remove,
> +};
> +module_platform_driver(pef2256_driver);
> +
> +struct regmap *pef2256_get_regmap(struct pef2256 *pef2256)
> +{
> +	return pef2256->regmap;
> +}
> +EXPORT_SYMBOL_GPL(pef2256_get_regmap);
> +
> +MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
> +MODULE_DESCRIPTION("PEF2256 driver");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/framer/pef2256.h b/include/linux/framer/pef2256.h
> new file mode 100644
> index 000000000000..71d80af58c40
> --- /dev/null
> +++ b/include/linux/framer/pef2256.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * PEF2256 consumer API
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +#ifndef __PEF2256_H__
> +#define __PEF2256_H__
> +
> +#include <linux/types.h>
> +
> +struct pef2256;
> +struct regmap;
> +
> +/* Retrieve the PEF2256 regmap */
> +struct regmap *pef2256_get_regmap(struct pef2256 *pef2256);
> +
> +/* PEF2256 hardware versions */
> +enum pef2256_version {
> +	PEF2256_VERSION_UNKNOWN,
> +	PEF2256_VERSION_1_2,
> +	PEF2256_VERSION_2_1,
> +	PEF2256_VERSION_2_2,
> +};
> +
> +/* Get the PEF2256 hardware version */
> +enum pef2256_version pef2256_get_version(struct pef2256 *pef2256);
> +
> +#endif /* __PEF2256_H__ */
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Re: [PATCH v2 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer

[Andrew Lunn]

> The generic framer has:
>  - 2 consumers (QMC HDLC drv and codec)
>  - 1 provider (PEF2256)
> 
> So, the design is the following:
>                         +------------------+           +---------+
>                         | QMC              | <- TDM -> | PEF2256 | <-> E1
>      +---------+        |  +-------------+ |           |         |
>      | CPU DAI | <-data--> | QMC channel | |           |         |
>      +---------+        |  +-------------+ |           |         |
> +--------------+        |  +-------------+ |           |         |
> | QMC HDLC drv | <-data--> | QMC channel | |           |         |
> +--------------+        |  +-------------+ |           |         |
>      ^                  +------------------+           |         |
>      |   +--------+     +-------------+                |         |
>      +-> | framer | <-> | PEF2256 drv | <- local bus ->|         |
>          |        |     |             |                +---------+
>      +-> |        |     |             |
>      |   +--------+     |  +-------+  |
>      +-------------------> | codec |  |
>                         |  +-------+  |
>                         +-------------+

Thanks for adding the framer framework. I did not look into all the
details, but the basic design looks good.

	 Andrew

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Linus Walleij]

Hi Herve,

thanks for your patch!

First: is this patch something we could merge separately? I don't see
any dependency on the other patches.

On Wed, Jul 26, 2023 at 5:04 PM Herve Codina <herve.codina@bootlin.com> wrote:

> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
>
> This pinmux support handles the pin muxing part (pins RP(A..D) and pins
> XP(A..D)) of the PEF2256.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

So it is a bridge chip? Please use that terminology since Linux
DRM often talks about bridges.

> +++ b/drivers/pinctrl/pinctrl-pef2256-regs.h
(...)
> +#include "linux/bitfield.h"

Really? I don't think there is such a file there.

Do you mean <linux/bitfield.h> and does this even compile?

> diff --git a/drivers/pinctrl/pinctrl-pef2256.c b/drivers/pinctrl/pinctrl-pef2256.c
(...)
> +struct pef2256_pinctrl {
> +       struct device *dev;
> +       struct regmap *regmap;
> +       enum pef2256_version version;
> +       struct {
> +               struct pinctrl_desc pctrl_desc;
> +               const struct pef2256_function_desc *functions;
> +               unsigned int nfunctions;
> +       } pinctrl;

Uh anonymous struct... can't you just define the struct separately
with a name? Or fold it into struct pef2256_pinctrl without the
additional struct? Thanks.

Otherwise it looks neat!

Yours,
Linus Walleij

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Linus Walleij]

On Mon, Aug 7, 2023 at 3:05 PM Linus Walleij <linus.walleij@linaro.org> wrote:

> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> So it is a bridge chip? Please use that terminology since Linux
> DRM often talks about bridges.

Replying to self: no it's not a bridge, it's a WAN thingy.

So perhaps write that this is a WAN interface adapter chip.

Yours,
Linus Walleij

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Andrew Lunn]

On Mon, Aug 07, 2023 at 03:06:42PM +0200, Linus Walleij wrote:
> On Mon, Aug 7, 2023 at 3:05 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> 
> > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> >
> > So it is a bridge chip? Please use that terminology since Linux
> > DRM often talks about bridges.
> 
> Replying to self: no it's not a bridge, it's a WAN thingy.
> 
> So perhaps write that this is a WAN interface adapter chip.

Hi Linus

In the E1/T1/J1 world, framer is a well understood concept. Maybe the
text needs a bit more background information to explain what this is
to somebody who does not have an old school telecoms background.

   Andrew

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Herve Codina]

Hi Linus, Andrew,

On Mon, 7 Aug 2023 15:17:11 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> On Mon, Aug 07, 2023 at 03:06:42PM +0200, Linus Walleij wrote:
> > On Mon, Aug 7, 2023 at 3:05 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> >   
> > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>  
> > >
> > > So it is a bridge chip? Please use that terminology since Linux
> > > DRM often talks about bridges.  
> > 
> > Replying to self: no it's not a bridge, it's a WAN thingy.
> > 
> > So perhaps write that this is a WAN interface adapter chip.  
> 
> Hi Linus
> 
> In the E1/T1/J1 world, framer is a well understood concept. Maybe the
> text needs a bit more background information to explain what this is
> to somebody who does not have an old school telecoms background.
> 
>    Andrew

Maybe I can add in my commit log:
--- 8< ---
This kind of component can be found in old telecommunication system.
It was used to digital transmission of many simultaneous telephone calls
by time-division multiplexing. Also using HDLC protocol, WAN networks
can be reached through the framer.
--- 8< ---

Do you think it will be better ?

Regards,
Hervé Codina

-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Mark Brown]

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On Mon, Aug 07, 2023 at 03:05:15PM +0200, Linus Walleij wrote:
> On Wed, Jul 26, 2023 at 5:04 PM Herve Codina <herve.codina@bootlin.com> wrote:

> > +#include "linux/bitfield.h"

> Really? I don't think there is such a file there.

> Do you mean <linux/bitfield.h> and does this even compile?

#include "" means "try the local directory first then fall back to
system includes" so it'll work, it picks up extra stuff on top of what
<> does.  There's a stylistic issue though.

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Linus Walleij]

On Mon, Aug 7, 2023 at 3:10 PM Mark Brown <broonie@kernel.org> wrote:
> On Mon, Aug 07, 2023 at 03:05:15PM +0200, Linus Walleij wrote:
> > On Wed, Jul 26, 2023 at 5:04 PM Herve Codina <herve.codina@bootlin.com> wrote:
>
> > > +#include "linux/bitfield.h"
>
> > Really? I don't think there is such a file there.
>
> > Do you mean <linux/bitfield.h> and does this even compile?
>
> #include "" means "try the local directory first then fall back to
> system includes" so it'll work, it picks up extra stuff on top of what
> <> does.  There's a stylistic issue though.

Wow that's a neat trick, I learn something new every day!

But we probably wanna be sure to get the system include.

Yours,
Linus Walleij

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Herve Codina]

Hi Linus,

On Mon, 7 Aug 2023 15:05:15 +0200
Linus Walleij <linus.walleij@linaro.org> wrote:

> Hi Herve,
> 
> thanks for your patch!
> 
> First: is this patch something we could merge separately? I don't see
> any dependency on the other patches.

It depends on pef2256:
in drivers/pinctrl/Kconfig:
--- 8< ---
+config PINCTRL_PEF2256
+	tristate "Lantiq PEF2256 (FALC56) pin controller driver"
+	depends on OF && FRAMER_PEF2256
--- 8< ---
in drivers/pinctrl/pinctrl-pef2256.c
--- 8< ---
+#include <linux/framer/pef2256.h>
--- 8< ---

All the pef2256 it depends on is provided by
 path 23/28 "net: wan: framer: Add support for the Lantiq PEF2256 framer"

> 
> On Wed, Jul 26, 2023 at 5:04 PM Herve Codina <herve.codina@bootlin.com> wrote:
> 
> > The Lantiq PEF2256 is a framer and line interface component designed to
> > fulfill all required interfacing between an analog E1/T1/J1 line and the
> > digital PCM system highway/H.100 bus.
> >
> > This pinmux support handles the pin muxing part (pins RP(A..D) and pins
> > XP(A..D)) of the PEF2256.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>  
> 
> So it is a bridge chip? Please use that terminology since Linux
> DRM often talks about bridges.
> 
> > +++ b/drivers/pinctrl/pinctrl-pef2256-regs.h  
> (...)
> > +#include "linux/bitfield.h"  
> 
> Really? I don't think there is such a file there.
> 
> Do you mean <linux/bitfield.h> and does this even compile?

Yes and it compiles (even with quoted included file).
I will be changed to <linux/bitfield.h> in the next interation.

> 
> > diff --git a/drivers/pinctrl/pinctrl-pef2256.c b/drivers/pinctrl/pinctrl-pef2256.c  
> (...)
> > +struct pef2256_pinctrl {
> > +       struct device *dev;
> > +       struct regmap *regmap;
> > +       enum pef2256_version version;
> > +       struct {
> > +               struct pinctrl_desc pctrl_desc;
> > +               const struct pef2256_function_desc *functions;
> > +               unsigned int nfunctions;
> > +       } pinctrl;  
> 
> Uh anonymous struct... can't you just define the struct separately
> with a name? Or fold it into struct pef2256_pinctrl without the
> additional struct? Thanks.

I will fold it into struct pef2256_pinctrl in the next iteration.

Thanks
Hervé

> 
> Otherwise it looks neat!
> 
> Yours,
> Linus Walleij

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Re: [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
> 
> This pinmux support handles the pin muxing part (pins RP(A..D) and pins
> XP(A..D)) of the PEF2256.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/pinctrl/Kconfig                |  14 ++
>   drivers/pinctrl/Makefile               |   1 +
>   drivers/pinctrl/pinctrl-pef2256-regs.h |  65 ++++++
>   drivers/pinctrl/pinctrl-pef2256.c      | 310 +++++++++++++++++++++++++
>   4 files changed, 390 insertions(+)
>   create mode 100644 drivers/pinctrl/pinctrl-pef2256-regs.h
>   create mode 100644 drivers/pinctrl/pinctrl-pef2256.c
> 
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 57d57af1f624..a3aa96b59c97 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -377,6 +377,20 @@ config PINCTRL_PALMAS
>   	  open drain configuration for the Palmas series devices like
>   	  TPS65913, TPS80036 etc.
>   
> +config PINCTRL_PEF2256
> +	tristate "Lantiq PEF2256 (FALC56) pin controller driver"
> +	depends on OF && FRAMER_PEF2256
> +	select PINMUX
> +	select GENERIC_PINCONF
> +	help
> +	  This option enables the pin controller support for the Lantiq PEF2256
> +	  framer, also known as FALC56.
> +
> +	  If unsure, say N.
> +
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called pinctrl-pef2256.
> +
>   config PINCTRL_PIC32
>   	bool "Microchip PIC32 pin controller driver"
>   	depends on OF
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 482b391b5deb..8f211f7671a8 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_PINCTRL_MLXBF3)	+= pinctrl-mlxbf3.o
>   obj-$(CONFIG_PINCTRL_OCELOT)	+= pinctrl-ocelot.o
>   obj-$(CONFIG_PINCTRL_OXNAS)	+= pinctrl-oxnas.o
>   obj-$(CONFIG_PINCTRL_PALMAS)	+= pinctrl-palmas.o
> +obj-$(CONFIG_PINCTRL_PEF2256)	+= pinctrl-pef2256.o
>   obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl-pic32.o
>   obj-$(CONFIG_PINCTRL_PISTACHIO)	+= pinctrl-pistachio.o
>   obj-$(CONFIG_PINCTRL_RK805)	+= pinctrl-rk805.o
> diff --git a/drivers/pinctrl/pinctrl-pef2256-regs.h b/drivers/pinctrl/pinctrl-pef2256-regs.h
> new file mode 100644
> index 000000000000..586d94007e24
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-pef2256-regs.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * PEF2256 pinctrl registers definition
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +#ifndef __PEF2256_PINCTRL_REGS_H__
> +#define __PEF2256_PINCTRL_REGS_H__
> +
> +#include "linux/bitfield.h"
> +
> +/* Port Configuration 1..4 */
> +#define PEF2256_PC1		  0x80
> +#define PEF2256_PC2		  0x81
> +#define PEF2256_PC3		  0x82
> +#define PEF2256_PC4		  0x83
> +#define PEF2256_12_PC_RPC_MASK	  GENMASK(6, 4)
> +#define PEF2256_12_PC_RPC_SYPR	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x0)
> +#define PEF2256_12_PC_RPC_RFM	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x1)
> +#define PEF2256_12_PC_RPC_RFMB	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x2)
> +#define PEF2256_12_PC_RPC_RSIGM	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x3)
> +#define PEF2256_12_PC_RPC_RSIG	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x4)
> +#define PEF2256_12_PC_RPC_DLR	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x5)
> +#define PEF2256_12_PC_RPC_FREEZE  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x6)
> +#define PEF2256_12_PC_RPC_RFSP	  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x7)
> +#define PEF2256_12_PC_XPC_MASK    GENMASK(4, 0)
> +#define PEF2256_12_PC_XPC_SYPX	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x0)
> +#define PEF2256_12_PC_XPC_XFMS	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x1)
> +#define PEF2256_12_PC_XPC_XSIG	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x2)
> +#define PEF2256_12_PC_XPC_TCLK	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x3)
> +#define PEF2256_12_PC_XPC_XMFB	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x4)
> +#define PEF2256_12_PC_XPC_XSIGM	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x5)
> +#define PEF2256_12_PC_XPC_DLX	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x6)
> +#define PEF2256_12_PC_XPC_XCLK	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x7)
> +#define PEF2256_12_PC_XPC_XLT	  FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x8)
> +#define PEF2256_2X_PC_RPC_MASK	  GENMASK(7, 4)
> +#define PEF2256_2X_PC_RPC_SYPR	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x0)
> +#define PEF2256_2X_PC_RPC_RFM	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x1)
> +#define PEF2256_2X_PC_RPC_RFMB	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x2)
> +#define PEF2256_2X_PC_RPC_RSIGM	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x3)
> +#define PEF2256_2X_PC_RPC_RSIG	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x4)
> +#define PEF2256_2X_PC_RPC_DLR	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x5)
> +#define PEF2256_2X_PC_RPC_FREEZE  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x6)
> +#define PEF2256_2X_PC_RPC_RFSP	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x7)
> +#define PEF2256_2X_PC_RPC_GPI	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x9)
> +#define PEF2256_2X_PC_RPC_GPOH	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xa)
> +#define PEF2256_2X_PC_RPC_GPOL	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xb)
> +#define PEF2256_2X_PC_RPC_LOS	  FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xc)
> +#define PEF2256_2X_PC_XPC_MASK	  GENMASK(3, 0)
> +#define PEF2256_2X_PC_XPC_SYPX	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x0)
> +#define PEF2256_2X_PC_XPC_XFMS	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x1)
> +#define PEF2256_2X_PC_XPC_XSIG	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x2)
> +#define PEF2256_2X_PC_XPC_TCLK	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x3)
> +#define PEF2256_2X_PC_XPC_XMFB	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x4)
> +#define PEF2256_2X_PC_XPC_XSIGM	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x5)
> +#define PEF2256_2X_PC_XPC_DLX	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x6)
> +#define PEF2256_2X_PC_XPC_XCLK	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x7)
> +#define PEF2256_2X_PC_XPC_XLT	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x8)
> +#define PEF2256_2X_PC_XPC_GPI	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x9)
> +#define PEF2256_2X_PC_XPC_GPOH	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0xa)
> +#define PEF2256_2X_PC_XPC_GPOL	  FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0xb)
> +
> +#endif /* __PEF2256_PINCTRL_REGS_H__ */
> diff --git a/drivers/pinctrl/pinctrl-pef2256.c b/drivers/pinctrl/pinctrl-pef2256.c
> new file mode 100644
> index 000000000000..90f611f6cc12
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-pef2256.c
> @@ -0,0 +1,310 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PEF2256 also known as FALC56 driver
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#include <linux/framer/pef2256.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include "pinctrl-pef2256-regs.h"
> +
> +struct pef2256_pinreg_desc {
> +	int offset;
> +	u8 mask;
> +};
> +
> +struct pef2256_function_desc {
> +	const char *name;
> +	const char * const*groups;
> +	unsigned int ngroups;
> +	u8 func_val;
> +};
> +
> +struct pef2256_pinctrl {
> +	struct device *dev;
> +	struct regmap *regmap;
> +	enum pef2256_version version;
> +	struct {
> +		struct pinctrl_desc pctrl_desc;
> +		const struct pef2256_function_desc *functions;
> +		unsigned int nfunctions;
> +	} pinctrl;
> +};
> +
> +static int pef2256_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	/* We map 1 group <-> 1 pin */
> +	return pef2256->pinctrl.pctrl_desc.npins;
> +}
> +
> +static const char *pef2256_get_group_name(struct pinctrl_dev *pctldev,
> +					  unsigned int selector)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	/* We map 1 group <-> 1 pin */
> +	return pef2256->pinctrl.pctrl_desc.pins[selector].name;
> +}
> +
> +static int pef2256_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
> +				  const unsigned int **pins,
> +				  unsigned int *num_pins)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	/* We map 1 group <-> 1 pin */
> +	*pins = &pef2256->pinctrl.pctrl_desc.pins[selector].number;
> +	*num_pins = 1;
> +
> +	return 0;
> +}
> +
> +static const struct pinctrl_ops pef2256_pctlops = {
> +	.get_groups_count	= pef2256_get_groups_count,
> +	.get_group_name		= pef2256_get_group_name,
> +	.get_group_pins		= pef2256_get_group_pins,
> +	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
> +	.dt_free_map		= pinconf_generic_dt_free_map,
> +};
> +
> +static int pef2256_get_functions_count(struct pinctrl_dev *pctldev)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return pef2256->pinctrl.nfunctions;
> +}
> +
> +static const char *pef2256_get_function_name(struct pinctrl_dev *pctldev,
> +					     unsigned int selector)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	return pef2256->pinctrl.functions[selector].name;
> +}
> +
> +static int pef2256_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
> +				       const char * const **groups,
> +				       unsigned * const num_groups)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +
> +	*groups = pef2256->pinctrl.functions[selector].groups;
> +	*num_groups = pef2256->pinctrl.functions[selector].ngroups;
> +	return 0;
> +}
> +
> +static int pef2256_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
> +			   unsigned int group_selector)
> +{
> +	struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
> +	const struct pef2256_pinreg_desc *pinreg_desc;
> +	u8 func_val;
> +
> +	/* We map 1 group <-> 1 pin */
> +	pinreg_desc = pef2256->pinctrl.pctrl_desc.pins[group_selector].drv_data;
> +	func_val = pef2256->pinctrl.functions[func_selector].func_val;
> +
> +	return regmap_update_bits(pef2256->regmap, pinreg_desc->offset,
> +				  pinreg_desc->mask, func_val);
> +}
> +
> +static const struct pinmux_ops pef2256_pmxops = {
> +	.get_functions_count	= pef2256_get_functions_count,
> +	.get_function_name	= pef2256_get_function_name,
> +	.get_function_groups	= pef2256_get_function_groups,
> +	.set_mux		= pef2256_set_mux,
> +};
> +
> +#define PEF2256_PINCTRL_PIN(_number, _name, _offset, _mask) { \
> +	.number = _number, \
> +	.name = _name, \
> +	.drv_data = &(struct pef2256_pinreg_desc) { \
> +		.offset = _offset, \
> +		.mask = _mask, \
> +	}, \
> +}
> +
> +static const struct pinctrl_pin_desc pef2256_v12_pins[] = {
> +	PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_12_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_12_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_12_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_12_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_12_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_12_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_12_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_12_PC_XPC_MASK),
> +};
> +
> +static const struct pinctrl_pin_desc pef2256_v2x_pins[] = {
> +	PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_2X_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_2X_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_2X_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_2X_PC_RPC_MASK),
> +	PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_2X_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_2X_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_2X_PC_XPC_MASK),
> +	PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_2X_PC_XPC_MASK),
> +};
> +
> +static const char *const pef2256_rp_groups[] = { "RPA", "RPB", "RPC", "RPD" };
> +static const char *const pef2256_xp_groups[] = { "XPA", "XPB", "XPC", "XPD" };
> +static const char *const pef2256_all_groups[] = { "RPA", "RPB", "RPC", "RPD",
> +						  "XPA", "XPB", "XPC", "XPD" };
> +
> +#define PEF2256_FUNCTION(_name, _func_val, _groups) { \
> +	.name = _name, \
> +	.groups = _groups, \
> +	.ngroups = ARRAY_SIZE(_groups), \
> +	.func_val = _func_val, \
> +}
> +
> +static const struct pef2256_function_desc pef2256_v2x_functions[] = {
> +	PEF2256_FUNCTION("SYPR",   PEF2256_2X_PC_RPC_SYPR,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFM",    PEF2256_2X_PC_RPC_RFM,    pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFMB",   PEF2256_2X_PC_RPC_RFMB,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("RSIGM",  PEF2256_2X_PC_RPC_RSIGM,  pef2256_rp_groups),
> +	PEF2256_FUNCTION("RSIG",   PEF2256_2X_PC_RPC_RSIG,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("DLR",    PEF2256_2X_PC_RPC_DLR,    pef2256_rp_groups),
> +	PEF2256_FUNCTION("FREEZE", PEF2256_2X_PC_RPC_FREEZE, pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFSP",   PEF2256_2X_PC_RPC_RFSP,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("LOS",    PEF2256_2X_PC_RPC_LOS,    pef2256_rp_groups),
> +
> +	PEF2256_FUNCTION("SYPX",  PEF2256_2X_PC_XPC_SYPX,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XFMS",  PEF2256_2X_PC_XPC_XFMS,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XSIG",  PEF2256_2X_PC_XPC_XSIG,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("TCLK",  PEF2256_2X_PC_XPC_TCLK,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XMFB",  PEF2256_2X_PC_XPC_XMFB,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XSIGM", PEF2256_2X_PC_XPC_XSIGM, pef2256_xp_groups),
> +	PEF2256_FUNCTION("DLX",   PEF2256_2X_PC_XPC_DLX,   pef2256_xp_groups),
> +	PEF2256_FUNCTION("XCLK",  PEF2256_2X_PC_XPC_XCLK,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XLT",   PEF2256_2X_PC_XPC_XLT,   pef2256_xp_groups),
> +
> +	PEF2256_FUNCTION("GPI",  PEF2256_2X_PC_RPC_GPI | PEF2256_2X_PC_XPC_GPI,
> +			 pef2256_all_groups),
> +	PEF2256_FUNCTION("GPOH", PEF2256_2X_PC_RPC_GPOH | PEF2256_2X_PC_XPC_GPOH,
> +			 pef2256_all_groups),
> +	PEF2256_FUNCTION("GPOL", PEF2256_2X_PC_RPC_GPOL | PEF2256_2X_PC_XPC_GPOL,
> +			 pef2256_all_groups),
> +};
> +
> +static const struct pef2256_function_desc pef2256_v12_functions[] = {
> +	PEF2256_FUNCTION("SYPR",   PEF2256_12_PC_RPC_SYPR,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFM",    PEF2256_12_PC_RPC_RFM,    pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFMB",   PEF2256_12_PC_RPC_RFMB,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("RSIGM",  PEF2256_12_PC_RPC_RSIGM,  pef2256_rp_groups),
> +	PEF2256_FUNCTION("RSIG",   PEF2256_12_PC_RPC_RSIG,   pef2256_rp_groups),
> +	PEF2256_FUNCTION("DLR",    PEF2256_12_PC_RPC_DLR,    pef2256_rp_groups),
> +	PEF2256_FUNCTION("FREEZE", PEF2256_12_PC_RPC_FREEZE, pef2256_rp_groups),
> +	PEF2256_FUNCTION("RFSP",   PEF2256_12_PC_RPC_RFSP,   pef2256_rp_groups),
> +
> +	PEF2256_FUNCTION("SYPX",  PEF2256_12_PC_XPC_SYPX,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XFMS",  PEF2256_12_PC_XPC_XFMS,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XSIG",  PEF2256_12_PC_XPC_XSIG,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("TCLK",  PEF2256_12_PC_XPC_TCLK,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XMFB",  PEF2256_12_PC_XPC_XMFB,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XSIGM", PEF2256_12_PC_XPC_XSIGM, pef2256_xp_groups),
> +	PEF2256_FUNCTION("DLX",   PEF2256_12_PC_XPC_DLX,   pef2256_xp_groups),
> +	PEF2256_FUNCTION("XCLK",  PEF2256_12_PC_XPC_XCLK,  pef2256_xp_groups),
> +	PEF2256_FUNCTION("XLT",   PEF2256_12_PC_XPC_XLT,   pef2256_xp_groups),
> +};
> +
> +static int pef2256_register_pinctrl(struct pef2256_pinctrl *pef2256)
> +{
> +	struct pinctrl_dev	*pctrl;
> +
> +	pef2256->pinctrl.pctrl_desc.name    = dev_name(pef2256->dev);
> +	pef2256->pinctrl.pctrl_desc.owner   = THIS_MODULE;
> +	pef2256->pinctrl.pctrl_desc.pctlops = &pef2256_pctlops;
> +	pef2256->pinctrl.pctrl_desc.pmxops  = &pef2256_pmxops;
> +	if (pef2256->version == PEF2256_VERSION_1_2) {
> +		pef2256->pinctrl.pctrl_desc.pins  = pef2256_v12_pins;
> +		pef2256->pinctrl.pctrl_desc.npins = ARRAY_SIZE(pef2256_v12_pins);
> +		pef2256->pinctrl.functions  = pef2256_v12_functions;
> +		pef2256->pinctrl.nfunctions = ARRAY_SIZE(pef2256_v12_functions);
> +	} else {
> +		pef2256->pinctrl.pctrl_desc.pins  = pef2256_v2x_pins;
> +		pef2256->pinctrl.pctrl_desc.npins = ARRAY_SIZE(pef2256_v2x_pins);
> +		pef2256->pinctrl.functions  = pef2256_v2x_functions;
> +		pef2256->pinctrl.nfunctions = ARRAY_SIZE(pef2256_v2x_functions);
> +	}
> +
> +	pctrl = devm_pinctrl_register(pef2256->dev, &pef2256->pinctrl.pctrl_desc, pef2256);
> +	if (IS_ERR(pctrl)) {
> +		dev_err(pef2256->dev, "pinctrl driver registration failed\n");
> +		return PTR_ERR(pctrl);
> +	}
> +
> +	return 0;
> +}
> +
> +static void pef2256_reset_pinmux(struct pef2256_pinctrl *pef2256)
> +{
> +	u8 val;
> +	/*
> +	 * Reset values cannot be used.
> +	 * They define the SYPR/SYPX pin mux for all the RPx and XPx pins and
> +	 * Only one pin can be muxed to SYPR and one pin can be muxed to SYPX.
> +	 * Choose here an other reset value.
> +	 */
> +	if (pef2256->version == PEF2256_VERSION_1_2)
> +		val = PEF2256_12_PC_XPC_XCLK | PEF2256_12_PC_RPC_RFSP;
> +	else
> +		val = PEF2256_2X_PC_XPC_GPI | PEF2256_2X_PC_RPC_GPI;
> +
> +	regmap_write(pef2256->regmap, PEF2256_PC1, val);
> +	regmap_write(pef2256->regmap, PEF2256_PC2, val);
> +	regmap_write(pef2256->regmap, PEF2256_PC3, val);
> +	regmap_write(pef2256->regmap, PEF2256_PC4, val);
> +}
> +
> +static int pef2256_pinctrl_probe(struct platform_device *pdev)
> +{
> +	struct pef2256_pinctrl *pef2256_pinctrl;
> +	struct pef2256 *pef2256;
> +	int ret;
> +
> +	pef2256_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pef2256_pinctrl), GFP_KERNEL);
> +	if (!pef2256_pinctrl)
> +		return -ENOMEM;
> +
> +	device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
> +
> +	pef2256 = dev_get_drvdata(pdev->dev.parent);
> +
> +	pef2256_pinctrl->dev = &pdev->dev;
> +	pef2256_pinctrl->regmap = pef2256_get_regmap(pef2256);
> +	pef2256_pinctrl->version = pef2256_get_version(pef2256);
> +
> +	platform_set_drvdata(pdev, pef2256_pinctrl);
> +
> +	pef2256_reset_pinmux(pef2256_pinctrl);
> +	ret = pef2256_register_pinctrl(pef2256_pinctrl);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver pef2256_pinctrl_driver = {
> +	.driver = {
> +		.name = "lantiq-pef2256-pinctrl",
> +	},
> +	.probe = pef2256_pinctrl_probe,
> +};
> +module_platform_driver(pef2256_pinctrl_driver);
> +
> +MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
> +MODULE_DESCRIPTION("PEF2256 pin controller driver");
> +MODULE_LICENSE("GPL");
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Re: [PATCH v2 01/28] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration

[Christophe Leroy]

Le 26/07/2023 à 17:01, Herve Codina a écrit :
> Running sparse (make C=1) on tsa.c raises a lot of warning such as:
>    --- 8< ---
>    warning: incorrect type in assignment (different address spaces)
>       expected void *[noderef] si_regs
>       got void [noderef] __iomem *
>    --- 8< ---
> 
> Indeed, some variable were declared 'type *__iomem var' instead of
> 'type __iomem *var'.
> 
> Use the correct declaration to remove these warnings.
> 
> Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA")
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/tsa.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
> index 3646153117b3..e0527b9efd05 100644
> --- a/drivers/soc/fsl/qe/tsa.c
> +++ b/drivers/soc/fsl/qe/tsa.c
> @@ -98,9 +98,9 @@
>   #define TSA_SIRP	0x10
>   
>   struct tsa_entries_area {
> -	void *__iomem entries_start;
> -	void *__iomem entries_next;
> -	void *__iomem last_entry;
> +	void __iomem *entries_start;
> +	void __iomem *entries_next;
> +	void __iomem *last_entry;
>   };
>   
>   struct tsa_tdm {
> @@ -117,8 +117,8 @@ struct tsa_tdm {
>   
>   struct tsa {
>   	struct device *dev;
> -	void *__iomem si_regs;
> -	void *__iomem si_ram;
> +	void __iomem *si_regs;
> +	void __iomem *si_ram;
>   	resource_size_t si_ram_sz;
>   	spinlock_t	lock;
>   	int tdms; /* TSA_TDMx ORed */
> @@ -135,27 +135,27 @@ static inline struct tsa *tsa_serial_get_tsa(struct tsa_serial *tsa_serial)
>   	return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]);
>   }
>   
> -static inline void tsa_write32(void *__iomem addr, u32 val)
> +static inline void tsa_write32(void __iomem *addr, u32 val)
>   {
>   	iowrite32be(val, addr);
>   }
>   
> -static inline void tsa_write8(void *__iomem addr, u32 val)
> +static inline void tsa_write8(void __iomem *addr, u32 val)
>   {
>   	iowrite8(val, addr);
>   }
>   
> -static inline u32 tsa_read32(void *__iomem addr)
> +static inline u32 tsa_read32(void __iomem *addr)
>   {
>   	return ioread32be(addr);
>   }
>   
> -static inline void tsa_clrbits32(void *__iomem addr, u32 clr)
> +static inline void tsa_clrbits32(void __iomem *addr, u32 clr)
>   {
>   	tsa_write32(addr, tsa_read32(addr) & ~clr);
>   }
>   
> -static inline void tsa_clrsetbits32(void *__iomem addr, u32 clr, u32 set)
> +static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set)
>   {
>   	tsa_write32(addr, (tsa_read32(addr) & ~clr) | set);
>   }
> @@ -313,7 +313,7 @@ static u32 tsa_serial_id2csel(struct tsa *tsa, u32 serial_id)
>   static int tsa_add_entry(struct tsa *tsa, struct tsa_entries_area *area,
>   			 u32 count, u32 serial_id)
>   {
> -	void *__iomem addr;
> +	void __iomem *addr;
>   	u32 left;
>   	u32 val;
>   	u32 cnt;
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Re: [PATCH v2 02/28] soc: fsl: cpm1: qmc: Fix __iomem addresses declaration

[Christophe Leroy]

Le 26/07/2023 à 17:01, Herve Codina a écrit :
> Running sparse (make C=1) on qmc.c raises a lot of warning such as:
>    ...
>    warning: incorrect type in assignment (different address spaces)
>       expected struct cpm_buf_desc [usertype] *[noderef] __iomem bd
>       got struct cpm_buf_desc [noderef] [usertype] __iomem *txbd_free
>    ...
> 
> Indeed, some variable were declared 'type *__iomem var' instead of
> 'type __iomem *var'.
> 
> Use the correct declaration to remove these warnings.
> 
> Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 34 +++++++++++++++++-----------------
>   1 file changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index b3c292c9a14e..7ad0d77f1740 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -175,7 +175,7 @@ struct qmc_chan {
>   	struct list_head list;
>   	unsigned int id;
>   	struct qmc *qmc;
> -	void *__iomem s_param;
> +	void __iomem *s_param;
>   	enum qmc_mode mode;
>   	u64	tx_ts_mask;
>   	u64	rx_ts_mask;
> @@ -203,9 +203,9 @@ struct qmc_chan {
>   struct qmc {
>   	struct device *dev;
>   	struct tsa_serial *tsa_serial;
> -	void *__iomem scc_regs;
> -	void *__iomem scc_pram;
> -	void *__iomem dpram;
> +	void __iomem *scc_regs;
> +	void __iomem *scc_pram;
> +	void __iomem *dpram;
>   	u16 scc_pram_offset;
>   	cbd_t __iomem *bd_table;
>   	dma_addr_t bd_dma_addr;
> @@ -218,37 +218,37 @@ struct qmc {
>   	struct qmc_chan *chans[64];
>   };
>   
> -static inline void qmc_write16(void *__iomem addr, u16 val)
> +static inline void qmc_write16(void __iomem *addr, u16 val)
>   {
>   	iowrite16be(val, addr);
>   }
>   
> -static inline u16 qmc_read16(void *__iomem addr)
> +static inline u16 qmc_read16(void __iomem *addr)
>   {
>   	return ioread16be(addr);
>   }
>   
> -static inline void qmc_setbits16(void *__iomem addr, u16 set)
> +static inline void qmc_setbits16(void __iomem *addr, u16 set)
>   {
>   	qmc_write16(addr, qmc_read16(addr) | set);
>   }
>   
> -static inline void qmc_clrbits16(void *__iomem addr, u16 clr)
> +static inline void qmc_clrbits16(void __iomem *addr, u16 clr)
>   {
>   	qmc_write16(addr, qmc_read16(addr) & ~clr);
>   }
>   
> -static inline void qmc_write32(void *__iomem addr, u32 val)
> +static inline void qmc_write32(void __iomem *addr, u32 val)
>   {
>   	iowrite32be(val, addr);
>   }
>   
> -static inline u32 qmc_read32(void *__iomem addr)
> +static inline u32 qmc_read32(void __iomem *addr)
>   {
>   	return ioread32be(addr);
>   }
>   
> -static inline void qmc_setbits32(void *__iomem addr, u32 set)
> +static inline void qmc_setbits32(void __iomem *addr, u32 set)
>   {
>   	qmc_write32(addr, qmc_read32(addr) | set);
>   }
> @@ -318,7 +318,7 @@ int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
>   {
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	u16 ctrl;
>   	int ret;
>   
> @@ -374,7 +374,7 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
>   	void (*complete)(void *context);
>   	unsigned long flags;
>   	void *context;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	u16 ctrl;
>   
>   	/*
> @@ -425,7 +425,7 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
>   {
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	u16 ctrl;
>   	int ret;
>   
> @@ -488,7 +488,7 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
>   	void (*complete)(void *context, size_t size);
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	void *context;
>   	u16 datalen;
>   	u16 ctrl;
> @@ -663,7 +663,7 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan)
>   {
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	u16 ctrl;
>   
>   	spin_lock_irqsave(&chan->rx_lock, flags);
> @@ -694,7 +694,7 @@ static void qmc_chan_reset_tx(struct qmc_chan *chan)
>   {
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> -	cbd_t *__iomem bd;
> +	cbd_t __iomem *bd;
>   	u16 ctrl;
>   
>   	spin_lock_irqsave(&chan->tx_lock, flags);
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Re: [PATCH v2 03/28] soc: fsl: cpm1: qmc: Fix rx channel reset

[Christophe Leroy]

Le 26/07/2023 à 17:01, Herve Codina a écrit :
> The qmc_chan_reset_rx() set the is_rx_stopped flag. This leads to an
> inconsistent state in the following sequence.
>      qmc_chan_stop()
>      qmc_chan_reset()
> Indeed, after the qmc_chan_reset() call, the channel must still be
> stopped. Only a qmc_chan_start() call can move the channel from stopped
> state to started state.
> 
> Fix the issue removing the is_rx_stopped flag setting from
> qmc_chan_reset()
> 
> Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 7ad0d77f1740..8dc73cc1a83b 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -685,7 +685,6 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan)
>   		    qmc_read16(chan->s_param + QMC_SPE_RBASE));
>   
>   	chan->rx_pending = 0;
> -	chan->is_rx_stopped = false;
>   
>   	spin_unlock_irqrestore(&chan->rx_lock, flags);
>   }
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Re: [PATCH v2 04/28] soc: fsl: cpm1: qmc: Extend the API to provide Rx status

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In HDLC mode, some status flags related to the data read transfer can be
> set by the hardware and need to be known by a QMC consumer for further
> analysis.
> 
> Extend the API in order to provide these transfer status flags at the
> read complete() call.
> 
> In TRANSPARENT mode, these flags have no meaning. Keep only one read
> complete() API and update the consumers working in transparent mode.
> In this case, the newly introduced flags parameter is simply unused.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c      | 29 +++++++++++++++++++++++++----
>   include/soc/fsl/qe/qmc.h      | 15 ++++++++++++++-
>   sound/soc/fsl/fsl_qmc_audio.c |  2 +-
>   3 files changed, 40 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 8dc73cc1a83b..2d2a9d88ba6c 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -166,7 +166,7 @@
>   struct qmc_xfer_desc {
>   	union {
>   		void (*tx_complete)(void *context);
> -		void (*rx_complete)(void *context, size_t length);
> +		void (*rx_complete)(void *context, size_t length, unsigned int flags);
>   	};
>   	void *context;
>   };
> @@ -421,7 +421,8 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
>   }
>   
>   int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> -			 void (*complete)(void *context, size_t length), void *context)
> +			 void (*complete)(void *context, size_t length, unsigned int flags),
> +			 void *context)
>   {
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
> @@ -454,6 +455,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
>   	xfer_desc->rx_complete = complete;
>   	xfer_desc->context = context;
>   
> +	/* Clear previous status flags */
> +	ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO |
> +		  QMC_BD_RX_AB | QMC_BD_RX_CR);
> +
>   	/* Activate the descriptor */
>   	ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB);
>   	wmb(); /* Be sure to flush data before descriptor activation */
> @@ -485,7 +490,7 @@ EXPORT_SYMBOL(qmc_chan_read_submit);
>   
>   static void qmc_chan_read_done(struct qmc_chan *chan)
>   {
> -	void (*complete)(void *context, size_t size);
> +	void (*complete)(void *context, size_t size, unsigned int flags);
>   	struct qmc_xfer_desc *xfer_desc;
>   	unsigned long flags;
>   	cbd_t __iomem *bd;
> @@ -527,7 +532,23 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
>   
>   		if (complete) {
>   			spin_unlock_irqrestore(&chan->rx_lock, flags);
> -			complete(context, datalen);
> +
> +			/*
> +			 * Avoid conversion between internal hardware flags and
> +			 * the software API flags.
> +			 * -> Be sure that the software API flags are consistent
> +			 *    with the hardware flags
> +			 */
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST  != QMC_BD_RX_L);
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST != QMC_BD_RX_F);
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF   != QMC_BD_RX_LG);
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA   != QMC_BD_RX_NO);
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT != QMC_BD_RX_AB);
> +			BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC   != QMC_BD_RX_CR);
> +
> +			complete(context, datalen,
> +				 ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG |
> +					 QMC_BD_RX_NO | QMC_BD_RX_AB | QMC_BD_RX_CR));
>   			spin_lock_irqsave(&chan->rx_lock, flags);
>   		}
>   
> diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
> index 3c61a50d2ae2..6f1d6cebc9fe 100644
> --- a/include/soc/fsl/qe/qmc.h
> +++ b/include/soc/fsl/qe/qmc.h
> @@ -9,6 +9,7 @@
>   #ifndef __SOC_FSL_QMC_H__
>   #define __SOC_FSL_QMC_H__
>   
> +#include <linux/bits.h>
>   #include <linux/types.h>
>   
>   struct device_node;
> @@ -56,8 +57,20 @@ int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param
>   int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
>   			  void (*complete)(void *context), void *context);
>   
> +/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
> + * No flags are available in transparent mode and the read complete() flags
> + * parameter has no meaning in transparent mode.
> + */
> +#define QMC_RX_FLAG_HDLC_LAST	BIT(11) /* Last in frame */
> +#define QMC_RX_FLAG_HDLC_FIRST	BIT(10) /* First in frame */
> +#define QMC_RX_FLAG_HDLC_OVF	BIT(5)  /* Data overflow */
> +#define QMC_RX_FLAG_HDLC_UNA	BIT(4)  /* Unaligned (ie. bits received not multiple of 8) */
> +#define QMC_RX_FLAG_HDLC_ABORT	BIT(3)  /* Received an abort sequence (seven consecutive ones) */
> +#define QMC_RX_FLAG_HDLC_CRC	BIT(2)  /* CRC error */
> +
>   int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> -			 void (*complete)(void *context, size_t length),
> +			 void (*complete)(void *context, size_t length,
> +					  unsigned int flags),
>   			 void *context);
>   
>   #define QMC_CHAN_READ  (1<<0)
> diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
> index 7cbb8e4758cc..5d745aae17a8 100644
> --- a/sound/soc/fsl/fsl_qmc_audio.c
> +++ b/sound/soc/fsl/fsl_qmc_audio.c
> @@ -99,7 +99,7 @@ static void qmc_audio_pcm_write_complete(void *context)
>   	snd_pcm_period_elapsed(prtd->substream);
>   }
>   
> -static void qmc_audio_pcm_read_complete(void *context, size_t length)
> +static void qmc_audio_pcm_read_complete(void *context, size_t length, unsigned int flags)
>   {
>   	struct qmc_dai_prtd *prtd = context;
>   	int ret;
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Re: [PATCH v2 06/28] net: wan: Add support for QMC HDLC

[Andrew Lunn]

> +static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
> +{
> +	return (struct qmc_hdlc *)dev_to_hdlc(netdev)->priv;

priv is a void *, so you don't need the cast.

     Andrew

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Re: [PATCH v2 06/28] net: wan: Add support for QMC HDLC

[Herve Codina]

On Tue, 1 Aug 2023 11:31:32 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > +static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
> > +{
> > +	return (struct qmc_hdlc *)dev_to_hdlc(netdev)->priv;  
> 
> priv is a void *, so you don't need the cast.
> 

Right, I will change in the next iteration.

Regards,
Hervé

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Re: [PATCH v2 06/28] net: wan: Add support for QMC HDLC

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The QMC HDLC driver provides support for HDLC using the QMC (QUICC
> Multichannel Controller) to transfer the HDLC data.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>


Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
> new file mode 100644
> index 000000000000..b4ebae963d39
> --- /dev/null
> +++ b/drivers/net/wan/fsl_qmc_hdlc.c

> +
> +static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
> +{
> +	return (struct qmc_hdlc *)dev_to_hdlc(netdev)->priv;

->priv is void* so no cast should be necessary.

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Re: [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks

[Andrew Lunn]

On Wed, Jul 26, 2023 at 05:02:04PM +0200, Herve Codina wrote:
> Available timeslots masks define timeslots available for the related
> channel. These timeslots are defined by the QMC binding.
> 
> Timeslots used are initialized to available timeslots but can be a
> subset of available timeslots.
> This prepares the dynamic timeslots management (ie. changing timeslots
> at runtime).
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  drivers/soc/fsl/qe/qmc.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 2d2a9d88ba6c..21ad7e79e7bd 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -177,7 +177,9 @@ struct qmc_chan {
>  	struct qmc *qmc;
>  	void __iomem *s_param;
>  	enum qmc_mode mode;
> +	u64	tx_ts_mask_avail;
>  	u64	tx_ts_mask;
> +	u64	rx_ts_mask_avail;
>  	u64	rx_ts_mask;

Is this for E1? So there is a maximum of 32 slots? A u32 would be
sufficient i think?

	   Andrew

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Re: [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks

[Herve Codina]

On Tue, 1 Aug 2023 11:33:39 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> On Wed, Jul 26, 2023 at 05:02:04PM +0200, Herve Codina wrote:
> > Available timeslots masks define timeslots available for the related
> > channel. These timeslots are defined by the QMC binding.
> > 
> > Timeslots used are initialized to available timeslots but can be a
> > subset of available timeslots.
> > This prepares the dynamic timeslots management (ie. changing timeslots
> > at runtime).
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  drivers/soc/fsl/qe/qmc.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> > index 2d2a9d88ba6c..21ad7e79e7bd 100644
> > --- a/drivers/soc/fsl/qe/qmc.c
> > +++ b/drivers/soc/fsl/qe/qmc.c
> > @@ -177,7 +177,9 @@ struct qmc_chan {
> >  	struct qmc *qmc;
> >  	void __iomem *s_param;
> >  	enum qmc_mode mode;
> > +	u64	tx_ts_mask_avail;
> >  	u64	tx_ts_mask;
> > +	u64	rx_ts_mask_avail;
> >  	u64	rx_ts_mask;  
> 
> Is this for E1? So there is a maximum of 32 slots? A u32 would be
> sufficient i think?
> 

The QMC can use up to 64 slots. So masks related to the QMC are on 64bits.
These masks are not specific to the E1 framer but really related to the QMC
capabilities.

Regards,
Hervé

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Re: [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> Available timeslots masks define timeslots available for the related
> channel. These timeslots are defined by the QMC binding.
> 
> Timeslots used are initialized to available timeslots but can be a
> subset of available timeslots.
> This prepares the dynamic timeslots management (ie. changing timeslots
> at runtime).
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 2d2a9d88ba6c..21ad7e79e7bd 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -177,7 +177,9 @@ struct qmc_chan {
>   	struct qmc *qmc;
>   	void __iomem *s_param;
>   	enum qmc_mode mode;
> +	u64	tx_ts_mask_avail;
>   	u64	tx_ts_mask;
> +	u64	rx_ts_mask_avail;
>   	u64	rx_ts_mask;
>   	bool is_reverse_data;
>   
> @@ -875,7 +877,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
>   			of_node_put(chan_np);
>   			return ret;
>   		}
> -		chan->tx_ts_mask = ts_mask;
> +		chan->tx_ts_mask_avail = ts_mask;
> +		chan->tx_ts_mask = chan->tx_ts_mask_avail;
>   
>   		ret = of_property_read_u64(chan_np, "fsl,rx-ts-mask", &ts_mask);
>   		if (ret) {
> @@ -884,7 +887,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
>   			of_node_put(chan_np);
>   			return ret;
>   		}
> -		chan->rx_ts_mask = ts_mask;
> +		chan->rx_ts_mask_avail = ts_mask;
> +		chan->rx_ts_mask = chan->rx_ts_mask_avail;
>   
>   		mode = "transparent";
>   		ret = of_property_read_string(chan_np, "fsl,operational-mode", &mode);
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Re: [PATCH v2 09/28] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa*

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> qmc_setup_tsa* are called once at initialisation.
> They initialize the QMC TSA table.
> In order to introduce setup function later on for dynamic timeslots
> management, rename the function to avoid later confusion.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 21ad7e79e7bd..64a11f5c6f85 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -919,7 +919,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
>   	return qmc_check_chans(qmc);
>   }
>   
> -static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *info)
> +static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *info)
>   {
>   	struct qmc_chan *chan;
>   	unsigned int i;
> @@ -961,7 +961,7 @@ static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *i
>   	return 0;
>   }
>   
> -static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info *info)
> +static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info *info)
>   {
>   	struct qmc_chan *chan;
>   	unsigned int i;
> @@ -1019,7 +1019,7 @@ static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info
>   	return 0;
>   }
>   
> -static int qmc_setup_tsa(struct qmc *qmc)
> +static int qmc_init_tsa(struct qmc *qmc)
>   {
>   	struct tsa_serial_info info;
>   	int ret;
> @@ -1030,12 +1030,12 @@ static int qmc_setup_tsa(struct qmc *qmc)
>   		return ret;
>   
>   	/*
> -	 * Setup one common 64 entries table or two 32 entries (one for Tx and
> -	 * one for Tx) according to assigned TS numbers.
> +	 * Initialize one common 64 entries table or two 32 entries (one for Tx
> +	 * and one for Tx) according to assigned TS numbers.
>   	 */
>   	return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
> -		qmc_setup_tsa_64rxtx(qmc, &info) :
> -		qmc_setup_tsa_32rx_32tx(qmc, &info);
> +		qmc_init_tsa_64rxtx(qmc, &info) :
> +		qmc_init_tsa_32rx_32tx(qmc, &info);
>   }
>   
>   static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan)
> @@ -1391,7 +1391,7 @@ static int qmc_probe(struct platform_device *pdev)
>   	qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3);
>   	qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8);
>   
> -	ret = qmc_setup_tsa(qmc);
> +	ret = qmc_init_tsa(qmc);
>   	if (ret)
>   		goto err_tsa_serial_disconnect;
>   
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Re: [PATCH v2 10/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa*

[Andrew Lunn]

> +static inline void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set)
> +{
> +	qmc_write16(addr, (qmc_read16(addr) & ~clr) | set);
> +}
> +

Please don't use inline in .c files. Let the compiler decide.

       Andrew

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Re: [PATCH v2 10/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa*

[Herve Codina]

On Tue, 1 Aug 2023 11:36:43 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > +static inline void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set)
> > +{
> > +	qmc_write16(addr, (qmc_read16(addr) & ~clr) | set);
> > +}
> > +  
> 
> Please don't use inline in .c files. Let the compiler decide.
> 
>        Andrew

Ok, I will remove the inline in the next iteration.
I will also remove the inline of all other similar functions (probably a
separate patch in the series).

Regards,
Hervé

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Re: [PATCH v2 10/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa*

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> Introduce the qmc_chan_setup_tsa* functions to setup entries related
> to the given channel.
> Use them during QMC channels setup.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 161 ++++++++++++++++++++++++++++++---------
>   1 file changed, 125 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 64a11f5c6f85..c5552a0b5b19 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -240,6 +240,11 @@ static inline void qmc_clrbits16(void __iomem *addr, u16 clr)
>   	qmc_write16(addr, qmc_read16(addr) & ~clr);
>   }
>   
> +static inline void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set)
> +{
> +	qmc_write16(addr, (qmc_read16(addr) & ~clr) | set);
> +}
> +
>   static inline void qmc_write32(void __iomem *addr, u32 val)
>   {
>   	iowrite32be(val, addr);
> @@ -562,6 +567,122 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
>   	spin_unlock_irqrestore(&chan->rx_lock, flags);
>   }
>   
> +static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_serial_info *info)
> +{
> +	unsigned int i;
> +	u16 curr;
> +	u16 val;
> +
> +	/*
> +	 * Use a common Tx/Rx 64 entries table.
> +	 * Tx and Rx related stuffs must be identical
> +	 */
> +	if (chan->tx_ts_mask != chan->rx_ts_mask) {
> +		dev_err(chan->qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id);
> +		return -EINVAL;
> +	}
> +
> +	val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
> +
> +	/* Check entries based on Rx stuff*/
> +	for (i = 0; i < info->nb_rx_ts; i++) {
> +		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2));
> +		if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
> +			dev_err(chan->qmc->dev, "chan %u TxRx entry %d already used\n",
> +				chan->id, i);
> +			return -EBUSY;
> +		}
> +	}
> +
> +	/* Set entries based on Rx stuff*/
> +	for (i = 0; i < info->nb_rx_ts; i++) {
> +		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> +				 ~QMC_TSA_WRAP, val);
> +	}
> +
> +	return 0;
> +}
> +
> +static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info)
> +{
> +	unsigned int i;
> +	u16 curr;
> +	u16 val;
> +
> +	/* Use a Tx 32 entries table and a Rx 32 entries table */
> +
> +	val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
> +
> +	/* Check entries based on Rx stuff */
> +	for (i = 0; i < info->nb_rx_ts; i++) {
> +		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2));
> +		if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
> +			dev_err(chan->qmc->dev, "chan %u Rx entry %d already used\n",
> +				chan->id, i);
> +			return -EBUSY;
> +		}
> +	}
> +	/* Check entries based on Tx stuff */
> +	for (i = 0; i < info->nb_tx_ts; i++) {
> +		if (!(chan->tx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2));
> +		if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
> +			dev_err(chan->qmc->dev, "chan %u Tx entry %d already used\n",
> +				chan->id, i);
> +			return -EBUSY;
> +		}
> +	}
> +
> +	/* Set entries based on Rx stuff */
> +	for (i = 0; i < info->nb_rx_ts; i++) {
> +		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> +				 ~QMC_TSA_WRAP, val);
> +	}
> +	/* Set entries based on Tx stuff */
> +	for (i = 0; i < info->nb_tx_ts; i++) {
> +		if (!(chan->tx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2),
> +				 ~QMC_TSA_WRAP, val);
> +	}
> +
> +	return 0;
> +}
> +
> +static int qmc_chan_setup_tsa(struct qmc_chan *chan)
> +{
> +	struct tsa_serial_info info;
> +	int ret;
> +
> +	/* Retrieve info from the TSA related serial */
> +	ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Setup one common 64 entries table or two 32 entries (one for Tx
> +	 * and one for Tx) according to assigned TS numbers.
> +	 */
> +	return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
> +		qmc_chan_setup_tsa_64rxtx(chan, &info) :
> +		qmc_chan_setup_tsa_32rx_32tx(chan, &info);
> +}
> +
>   static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
>   {
>   	return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E);
> @@ -921,7 +1042,6 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
>   
>   static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *info)
>   {
> -	struct qmc_chan *chan;
>   	unsigned int i;
>   	u16 val;
>   
> @@ -935,18 +1055,6 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *in
>   	for (i = 0; i < 64; i++)
>   		qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000);
>   
> -	/* Set entries based on Rx stuff*/
> -	list_for_each_entry(chan, &qmc->chan_head, list) {
> -		for (i = 0; i < info->nb_rx_ts; i++) {
> -			if (!(chan->rx_ts_mask & (((u64)1) << i)))
> -				continue;
> -
> -			val = QMC_TSA_VALID | QMC_TSA_MASK |
> -			      QMC_TSA_CHANNEL(chan->id);
> -			qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val);
> -		}
> -	}
> -
>   	/* Set Wrap bit on last entry */
>   	qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2),
>   		      QMC_TSA_WRAP);
> @@ -963,7 +1071,6 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *in
>   
>   static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info *info)
>   {
> -	struct qmc_chan *chan;
>   	unsigned int i;
>   	u16 val;
>   
> @@ -978,28 +1085,6 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info
>   		qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 0x0000);
>   	}
>   
> -	/* Set entries based on Rx and Tx stuff*/
> -	list_for_each_entry(chan, &qmc->chan_head, list) {
> -		/* Rx part */
> -		for (i = 0; i < info->nb_rx_ts; i++) {
> -			if (!(chan->rx_ts_mask & (((u64)1) << i)))
> -				continue;
> -
> -			val = QMC_TSA_VALID | QMC_TSA_MASK |
> -			      QMC_TSA_CHANNEL(chan->id);
> -			qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val);
> -		}
> -		/* Tx part */
> -		for (i = 0; i < info->nb_tx_ts; i++) {
> -			if (!(chan->tx_ts_mask & (((u64)1) << i)))
> -				continue;
> -
> -			val = QMC_TSA_VALID | QMC_TSA_MASK |
> -			      QMC_TSA_CHANNEL(chan->id);
> -			qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), val);
> -		}
> -	}
> -
>   	/* Set Wrap bit on last entries */
>   	qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2),
>   		      QMC_TSA_WRAP);
> @@ -1081,6 +1166,10 @@ static int qmc_setup_chan(struct qmc *qmc, struct qmc_chan *chan)
>   
>   	chan->qmc = qmc;
>   
> +	ret = qmc_chan_setup_tsa(chan);
> +	if (ret)
> +		return ret;
> +
>   	/* Set channel specific parameter base address */
>   	chan->s_param = qmc->dpram + (chan->id * 64);
>   	/* 16 bd per channel (8 rx and 8 tx) */
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Re: [PATCH v2 11/28] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans()

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The newly introduced qmc_chan_setup_tsa* functions check that the
> channel entries are not already used.
> These checks are also performed by qmc_check_chans() and are no more
> needed.
> 
> Remove them from qmc_check_chans().
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 20 --------------------
>   1 file changed, 20 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index c5552a0b5b19..33761c39aee1 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -884,10 +884,7 @@ EXPORT_SYMBOL(qmc_chan_reset);
>   static int qmc_check_chans(struct qmc *qmc)
>   {
>   	struct tsa_serial_info info;
> -	bool is_one_table = false;
>   	struct qmc_chan *chan;
> -	u64 tx_ts_mask = 0;
> -	u64 rx_ts_mask = 0;
>   	u64 tx_ts_assigned_mask;
>   	u64 rx_ts_assigned_mask;
>   	int ret;
> @@ -911,7 +908,6 @@ static int qmc_check_chans(struct qmc *qmc)
>   			dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned are not equal\n");
>   			return -EINVAL;
>   		}
> -		is_one_table = true;
>   	}
>   
>   	tx_ts_assigned_mask = info.nb_tx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_tx_ts) - 1;
> @@ -922,27 +918,11 @@ static int qmc_check_chans(struct qmc *qmc)
>   			dev_err(qmc->dev, "chan %u uses TSA unassigned Tx TS\n", chan->id);
>   			return -EINVAL;
>   		}
> -		if (tx_ts_mask & chan->tx_ts_mask) {
> -			dev_err(qmc->dev, "chan %u uses an already used Tx TS\n", chan->id);
> -			return -EINVAL;
> -		}
>   
>   		if (chan->rx_ts_mask > rx_ts_assigned_mask) {
>   			dev_err(qmc->dev, "chan %u uses TSA unassigned Rx TS\n", chan->id);
>   			return -EINVAL;
>   		}
> -		if (rx_ts_mask & chan->rx_ts_mask) {
> -			dev_err(qmc->dev, "chan %u uses an already used Rx TS\n", chan->id);
> -			return -EINVAL;
> -		}
> -
> -		if (is_one_table && (chan->tx_ts_mask != chan->rx_ts_mask)) {
> -			dev_err(qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id);
> -			return -EINVAL;
> -		}
> -
> -		tx_ts_mask |= chan->tx_ts_mask;
> -		rx_ts_mask |= chan->rx_ts_mask;
>   	}
>   
>   	return 0;
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Re: [PATCH v2 12/28] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans()

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The timeslots checked in qmc_check_chans() are the timeslots used.
> With the introduction of the available timeslots, the used timeslots
> are a subset of the available timeslots. The timeslots checked during
> the qmc_check_chans() call should be the available ones.
> 
> Simply update and check the available timeslots instead of the used
> timeslots in qmc_check_chans().
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>


Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>


> ---
>   drivers/soc/fsl/qe/qmc.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 33761c39aee1..82405915f2a4 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -914,13 +914,13 @@ static int qmc_check_chans(struct qmc *qmc)
>   	rx_ts_assigned_mask = info.nb_rx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_rx_ts) - 1;
>   
>   	list_for_each_entry(chan, &qmc->chan_head, list) {
> -		if (chan->tx_ts_mask > tx_ts_assigned_mask) {
> -			dev_err(qmc->dev, "chan %u uses TSA unassigned Tx TS\n", chan->id);
> +		if (chan->tx_ts_mask_avail > tx_ts_assigned_mask) {
> +			dev_err(qmc->dev, "chan %u can use TSA unassigned Tx TS\n", chan->id);
>   			return -EINVAL;
>   		}
>   
> -		if (chan->rx_ts_mask > rx_ts_assigned_mask) {
> -			dev_err(qmc->dev, "chan %u uses TSA unassigned Rx TS\n", chan->id);
> +		if (chan->rx_ts_mask_avail > rx_ts_assigned_mask) {
> +			dev_err(qmc->dev, "chan %u can use TSA unassigned Rx TS\n", chan->id);
>   			return -EINVAL;
>   		}
>   	}
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Re: [PATCH v2 13/28] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In order to allow runtime timeslot route changes, disabling channel TSA
> entries needs to be supported.
> 
> Add support for this new feature.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 20 +++++++++++---------
>   1 file changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 82405915f2a4..146eebc12737 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -567,7 +567,8 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
>   	spin_unlock_irqrestore(&chan->rx_lock, flags);
>   }
>   
> -static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_serial_info *info)
> +static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_serial_info *info,
> +				     bool enable)
>   {
>   	unsigned int i;
>   	u16 curr;
> @@ -603,13 +604,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_ser
>   			continue;
>   
>   		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> -				 ~QMC_TSA_WRAP, val);
> +				 ~QMC_TSA_WRAP, enable ? val : 0x0000);
>   	}
>   
>   	return 0;
>   }
>   
> -static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info)
> +static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info,
> +					bool enable)
>   {
>   	unsigned int i;
>   	u16 curr;
> @@ -650,7 +652,7 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
>   			continue;
>   
>   		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> -				 ~QMC_TSA_WRAP, val);
> +				 ~QMC_TSA_WRAP, enable ? val : 0x0000);
>   	}
>   	/* Set entries based on Tx stuff */
>   	for (i = 0; i < info->nb_tx_ts; i++) {
> @@ -658,13 +660,13 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
>   			continue;
>   
>   		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2),
> -				 ~QMC_TSA_WRAP, val);
> +				 ~QMC_TSA_WRAP, enable ? val : 0x0000);
>   	}
>   
>   	return 0;
>   }
>   
> -static int qmc_chan_setup_tsa(struct qmc_chan *chan)
> +static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
>   {
>   	struct tsa_serial_info info;
>   	int ret;
> @@ -679,8 +681,8 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan)
>   	 * and one for Tx) according to assigned TS numbers.
>   	 */
>   	return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
> -		qmc_chan_setup_tsa_64rxtx(chan, &info) :
> -		qmc_chan_setup_tsa_32rx_32tx(chan, &info);
> +		qmc_chan_setup_tsa_64rxtx(chan, &info, enable) :
> +		qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable);
>   }
>   
>   static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
> @@ -1146,7 +1148,7 @@ static int qmc_setup_chan(struct qmc *qmc, struct qmc_chan *chan)
>   
>   	chan->qmc = qmc;
>   
> -	ret = qmc_chan_setup_tsa(chan);
> +	ret = qmc_chan_setup_tsa(chan, true);
>   	if (ret)
>   		return ret;
>   
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Re: [PATCH v2 14/28] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The Tx and Rx entries for a given channel are set in one function.
> 
> In order to modify Rx entries and Tx entries independently of one other,
> split this function in one for the Rx part and one for the Tx part.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 49 ++++++++++++++++++++++++++++------------
>   1 file changed, 35 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 146eebc12737..c8ddd2a54bee 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -610,14 +610,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct tsa_ser
>   	return 0;
>   }
>   
> -static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info,
> -					bool enable)
> +static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct tsa_serial_info *info,
> +				   bool enable)
>   {
>   	unsigned int i;
>   	u16 curr;
>   	u16 val;
>   
> -	/* Use a Tx 32 entries table and a Rx 32 entries table */
> +	/* Use a Rx 32 entries table */
>   
>   	val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
>   
> @@ -633,6 +633,30 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
>   			return -EBUSY;
>   		}
>   	}
> +
> +	/* Set entries based on Rx stuff */
> +	for (i = 0; i < info->nb_rx_ts; i++) {
> +		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> +			continue;
> +
> +		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> +				 ~QMC_TSA_WRAP, enable ? val : 0x0000);
> +	}
> +
> +	return 0;
> +}
> +
> +static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa_serial_info *info,
> +				   bool enable)
> +{
> +	unsigned int i;
> +	u16 curr;
> +	u16 val;
> +
> +	/* Use a Tx 32 entries table */
> +
> +	val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
> +
>   	/* Check entries based on Tx stuff */
>   	for (i = 0; i < info->nb_tx_ts; i++) {
>   		if (!(chan->tx_ts_mask & (((u64)1) << i)))
> @@ -646,14 +670,6 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct tsa_
>   		}
>   	}
>   
> -	/* Set entries based on Rx stuff */
> -	for (i = 0; i < info->nb_rx_ts; i++) {
> -		if (!(chan->rx_ts_mask & (((u64)1) << i)))
> -			continue;
> -
> -		qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
> -				 ~QMC_TSA_WRAP, enable ? val : 0x0000);
> -	}
>   	/* Set entries based on Tx stuff */
>   	for (i = 0; i < info->nb_tx_ts; i++) {
>   		if (!(chan->tx_ts_mask & (((u64)1) << i)))
> @@ -680,9 +696,14 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
>   	 * Setup one common 64 entries table or two 32 entries (one for Tx
>   	 * and one for Tx) according to assigned TS numbers.
>   	 */
> -	return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
> -		qmc_chan_setup_tsa_64rxtx(chan, &info, enable) :
> -		qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable);
> +	if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32)
> +		return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> +
> +	ret = qmc_chan_setup_tsa_32rx(chan, &info, enable);
> +	if (ret)
> +		return ret;
> +
> +	return qmc_chan_setup_tsa_32tx(chan, &info, enable);
>   }
>   
>   static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
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Re: [PATCH v2 15/28] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In order to support runtime timeslot route changes, some operations will
> be different according the routing table used (common Rx and Tx table or
> one table for Rx and one for Tx).
> 
> The is_tsa_64rxtx flag is introduced to avoid extra computation to
> determine the table format each time we need it.
> It is set once at initialization.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index c8ddd2a54bee..dc113463fbc7 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -216,6 +216,7 @@ struct qmc {
>   	u16 __iomem *int_curr;
>   	dma_addr_t int_dma_addr;
>   	size_t int_size;
> +	bool is_tsa_64rxtx;
>   	struct list_head chan_head;
>   	struct qmc_chan *chans[64];
>   };
> @@ -696,7 +697,7 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
>   	 * Setup one common 64 entries table or two 32 entries (one for Tx
>   	 * and one for Tx) according to assigned TS numbers.
>   	 */
> -	if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32)
> +	if (chan->qmc->is_tsa_64rxtx)
>   		return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
>   
>   	ret = qmc_chan_setup_tsa_32rx(chan, &info, enable);
> @@ -1053,6 +1054,7 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *in
>   	 * Everything was previously checked, Tx and Rx related stuffs are
>   	 * identical -> Used Rx related stuff to build the table
>   	 */
> +	qmc->is_tsa_64rxtx = true;
>   
>   	/* Invalidate all entries */
>   	for (i = 0; i < 64; i++)
> @@ -1081,6 +1083,7 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info
>   	 * Use a Tx 32 entries table and a Rx 32 entries table.
>   	 * Everything was previously checked.
>   	 */
> +	qmc->is_tsa_64rxtx = false;
>   
>   	/* Invalidate all entries */
>   	for (i = 0; i < 32; i++) {
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Re: [PATCH v2 16/28] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In order to support runtime timeslot route changes, enable the
> channel timeslot entries at channel start() and disable them at
> channel stop().
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 175 ++++++++++++++++++++++++++++++++++++---
>   1 file changed, 163 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index dc113463fbc7..258a34641551 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -177,6 +177,7 @@ struct qmc_chan {
>   	struct qmc *qmc;
>   	void __iomem *s_param;
>   	enum qmc_mode mode;
> +	spinlock_t	ts_lock; /* Protect timeslots */
>   	u64	tx_ts_mask_avail;
>   	u64	tx_ts_mask;
>   	u64	rx_ts_mask_avail;
> @@ -265,6 +266,7 @@ static inline void qmc_setbits32(void __iomem *addr, u32 set)
>   int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
>   {
>   	struct tsa_serial_info tsa_info;
> +	unsigned long flags;
>   	int ret;
>   
>   	/* Retrieve info from the TSA related serial */
> @@ -272,6 +274,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
>   	if (ret)
>   		return ret;
>   
> +	spin_lock_irqsave(&chan->ts_lock, flags);
> +
>   	info->mode = chan->mode;
>   	info->rx_fs_rate = tsa_info.rx_fs_rate;
>   	info->rx_bit_rate = tsa_info.rx_bit_rate;
> @@ -280,6 +284,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
>   	info->tx_bit_rate = tsa_info.tx_bit_rate;
>   	info->nb_rx_ts = hweight64(chan->rx_ts_mask);
>   
> +	spin_unlock_irqrestore(&chan->ts_lock, flags);
> +
>   	return 0;
>   }
>   EXPORT_SYMBOL(qmc_chan_get_info);
> @@ -683,6 +689,40 @@ static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa_seria
>   	return 0;
>   }
>   
> +static int qmc_chan_setup_tsa_tx(struct qmc_chan *chan, bool enable)
> +{
> +	struct tsa_serial_info info;
> +	int ret;
> +
> +	/* Retrieve info from the TSA related serial */
> +	ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> +	if (ret)
> +		return ret;
> +
> +	/* Setup entries */
> +	if (chan->qmc->is_tsa_64rxtx)
> +		return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> +
> +	return qmc_chan_setup_tsa_32tx(chan, &info, enable);
> +}
> +
> +static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable)
> +{
> +	struct tsa_serial_info info;
> +	int ret;
> +
> +	/* Retrieve info from the TSA related serial */
> +	ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> +	if (ret)
> +		return ret;
> +
> +	/* Setup entries */
> +	if (chan->qmc->is_tsa_64rxtx)
> +		return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> +
> +	return qmc_chan_setup_tsa_32rx(chan, &info, enable);
> +}
> +
>   static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
>   {
>   	struct tsa_serial_info info;
> @@ -719,6 +759,12 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
>   
>   	spin_lock_irqsave(&chan->rx_lock, flags);
>   
> +	if (chan->is_rx_stopped) {
> +		/* The channel is already stopped -> simply return ok */
> +		ret = 0;
> +		goto end;
> +	}
> +
>   	/* Send STOP RECEIVE command */
>   	ret = qmc_chan_command(chan, 0x0);
>   	if (ret) {
> @@ -729,6 +775,15 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
>   
>   	chan->is_rx_stopped = true;
>   
> +	if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) {
> +		ret = qmc_chan_setup_tsa_rx(chan, false);
> +		if (ret) {
> +			dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n",
> +				chan->id, ret);
> +			goto end;
> +		}
> +	}
> +
>   end:
>   	spin_unlock_irqrestore(&chan->rx_lock, flags);
>   	return ret;
> @@ -741,6 +796,12 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
>   
>   	spin_lock_irqsave(&chan->tx_lock, flags);
>   
> +	if (chan->is_tx_stopped) {
> +		/* The channel is already stopped -> simply return ok */
> +		ret = 0;
> +		goto end;
> +	}
> +
>   	/* Send STOP TRANSMIT command */
>   	ret = qmc_chan_command(chan, 0x1);
>   	if (ret) {
> @@ -751,37 +812,82 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
>   
>   	chan->is_tx_stopped = true;
>   
> +	if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) {
> +		ret = qmc_chan_setup_tsa_tx(chan, false);
> +		if (ret) {
> +			dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n",
> +				chan->id, ret);
> +			goto end;
> +		}
> +	}
> +
>   end:
>   	spin_unlock_irqrestore(&chan->tx_lock, flags);
>   	return ret;
>   }
>   
> +static int qmc_chan_start_rx(struct qmc_chan *chan);
> +
>   int qmc_chan_stop(struct qmc_chan *chan, int direction)
>   {
> -	int ret;
> +	bool is_rx_rollback_needed = false;
> +	unsigned long flags;
> +	int ret = 0;
> +
> +	spin_lock_irqsave(&chan->ts_lock, flags);
>   
>   	if (direction & QMC_CHAN_READ) {
> +		is_rx_rollback_needed = !chan->is_rx_stopped;
>   		ret = qmc_chan_stop_rx(chan);
>   		if (ret)
> -			return ret;
> +			goto end;
>   	}
>   
>   	if (direction & QMC_CHAN_WRITE) {
>   		ret = qmc_chan_stop_tx(chan);
> -		if (ret)
> -			return ret;
> +		if (ret) {
> +			/* Restart rx if needed */
> +			if (is_rx_rollback_needed)
> +				qmc_chan_start_rx(chan);
> +			goto end;
> +		}
>   	}
>   
> -	return 0;
> +end:
> +	spin_unlock_irqrestore(&chan->ts_lock, flags);
> +	return ret;
>   }
>   EXPORT_SYMBOL(qmc_chan_stop);
>   
> -static void qmc_chan_start_rx(struct qmc_chan *chan)
> +static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan);
> +
> +static int qmc_chan_start_rx(struct qmc_chan *chan)
>   {
>   	unsigned long flags;
> +	int ret;
>   
>   	spin_lock_irqsave(&chan->rx_lock, flags);
>   
> +	if (!chan->is_rx_stopped) {
> +		/* The channel is already started -> simply return ok */
> +		ret = 0;
> +		goto end;
> +	}
> +
> +	ret = qmc_chan_setup_tsa_rx(chan, true);
> +	if (ret) {
> +		dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n",
> +			chan->id, ret);
> +		goto end;
> +	}
> +
> +	ret = qmc_setup_chan_trnsync(chan->qmc, chan);
> +	if (ret) {
> +		dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n",
> +			chan->id, ret);
> +		goto end;
> +	}
> +
>   	/* Restart the receiver */
>   	if (chan->mode == QMC_TRANSPARENT)
>   		qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080);
> @@ -792,15 +898,38 @@ static void qmc_chan_start_rx(struct qmc_chan *chan)
>   
>   	chan->is_rx_stopped = false;
>   
> +end:
>   	spin_unlock_irqrestore(&chan->rx_lock, flags);
> +	return ret;
>   }
>   
> -static void qmc_chan_start_tx(struct qmc_chan *chan)
> +static int qmc_chan_start_tx(struct qmc_chan *chan)
>   {
>   	unsigned long flags;
> +	int ret;
>   
>   	spin_lock_irqsave(&chan->tx_lock, flags);
>   
> +	if (!chan->is_tx_stopped) {
> +		/* The channel is already started -> simply return ok */
> +		ret = 0;
> +		goto end;
> +	}
> +
> +	ret = qmc_chan_setup_tsa_tx(chan, true);
> +	if (ret) {
> +		dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n",
> +			chan->id, ret);
> +		goto end;
> +	}
> +
> +	ret = qmc_setup_chan_trnsync(chan->qmc, chan);
> +	if (ret) {
> +		dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n",
> +			chan->id, ret);
> +		goto end;
> +	}
> +
>   	/*
>   	 * Enable channel transmitter as it could be disabled if
>   	 * qmc_chan_reset() was called.
> @@ -812,18 +941,39 @@ static void qmc_chan_start_tx(struct qmc_chan *chan)
>   
>   	chan->is_tx_stopped = false;
>   
> +end:
>   	spin_unlock_irqrestore(&chan->tx_lock, flags);
> +	return ret;
>   }
>   
>   int qmc_chan_start(struct qmc_chan *chan, int direction)
>   {
> -	if (direction & QMC_CHAN_READ)
> -		qmc_chan_start_rx(chan);
> +	bool is_rx_rollback_needed = false;
> +	unsigned long flags;
> +	int ret = 0;
>   
> -	if (direction & QMC_CHAN_WRITE)
> -		qmc_chan_start_tx(chan);
> +	spin_lock_irqsave(&chan->ts_lock, flags);
>   
> -	return 0;
> +	if (direction & QMC_CHAN_READ) {
> +		is_rx_rollback_needed = chan->is_rx_stopped;
> +		ret = qmc_chan_start_rx(chan);
> +		if (ret)
> +			goto end;
> +	}
> +
> +	if (direction & QMC_CHAN_WRITE) {
> +		ret = qmc_chan_start_tx(chan);
> +		if (ret) {
> +			/* Restop rx if needed */
> +			if (is_rx_rollback_needed)
> +				qmc_chan_stop_rx(chan);
> +			goto end;
> +		}
> +	}
> +
> +end:
> +	spin_unlock_irqrestore(&chan->ts_lock, flags);
> +	return ret;
>   }
>   EXPORT_SYMBOL(qmc_chan_start);
>   
> @@ -992,6 +1142,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
>   		}
>   
>   		chan->id = chan_id;
> +		spin_lock_init(&chan->ts_lock);
>   		spin_lock_init(&chan->rx_lock);
>   		spin_lock_init(&chan->tx_lock);
>   
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Re: [PATCH v2 17/28] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan()

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> Timeslots setting is done at channel start() and stop().
> There is no more need to do that during setup_chan().
> 
> Simply remove timeslot setting from setup_chan().
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 28 ----------------------------
>   1 file changed, 28 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 258a34641551..b1883b9d2bae 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -723,30 +723,6 @@ static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable)
>   	return qmc_chan_setup_tsa_32rx(chan, &info, enable);
>   }
>   
> -static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
> -{
> -	struct tsa_serial_info info;
> -	int ret;
> -
> -	/* Retrieve info from the TSA related serial */
> -	ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> -	if (ret)
> -		return ret;
> -
> -	/*
> -	 * Setup one common 64 entries table or two 32 entries (one for Tx
> -	 * and one for Tx) according to assigned TS numbers.
> -	 */
> -	if (chan->qmc->is_tsa_64rxtx)
> -		return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> -
> -	ret = qmc_chan_setup_tsa_32rx(chan, &info, enable);
> -	if (ret)
> -		return ret;
> -
> -	return qmc_chan_setup_tsa_32tx(chan, &info, enable);
> -}
> -
>   static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
>   {
>   	return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E);
> @@ -1323,10 +1299,6 @@ static int qmc_setup_chan(struct qmc *qmc, struct qmc_chan *chan)
>   
>   	chan->qmc = qmc;
>   
> -	ret = qmc_chan_setup_tsa(chan, true);
> -	if (ret)
> -		return ret;
> -
>   	/* Set channel specific parameter base address */
>   	chan->s_param = qmc->dpram + (chan->id * 64);
>   	/* 16 bd per channel (8 rx and 8 tx) */
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Re: [PATCH v2 18/28] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> Introduce qmc_chan_{get,set}_ts_info() function to allow timeslots
> modification at runtime.
> 
> The modification is provided using qmc_chan_set_ts_info() and will be
> applied on next qmc_chan_start().
> qmc_chan_set_ts_info() must be called with the channel rx and/or tx
> stopped.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 51 ++++++++++++++++++++++++++++++++++++++++
>   include/soc/fsl/qe/qmc.h | 10 ++++++++
>   2 files changed, 61 insertions(+)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index b1883b9d2bae..e3953bc07b1f 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -290,6 +290,57 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
>   }
>   EXPORT_SYMBOL(qmc_chan_get_info);
>   
> +int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&chan->ts_lock, flags);
> +
> +	ts_info->rx_ts_mask_avail = chan->rx_ts_mask_avail;
> +	ts_info->tx_ts_mask_avail = chan->tx_ts_mask_avail;
> +	ts_info->rx_ts_mask = chan->rx_ts_mask;
> +	ts_info->tx_ts_mask = chan->tx_ts_mask;
> +
> +	spin_unlock_irqrestore(&chan->ts_lock, flags);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(qmc_chan_get_ts_info);
> +
> +int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info)
> +{
> +	unsigned long flags;
> +	int ret;
> +
> +	/* Only a subset of available timeslots is allowed */
> +	if ((ts_info->rx_ts_mask & chan->rx_ts_mask_avail) != ts_info->rx_ts_mask)
> +		return -EINVAL;
> +	if ((ts_info->tx_ts_mask & chan->tx_ts_mask_avail) != ts_info->tx_ts_mask)
> +		return -EINVAL;
> +
> +	/* In case of common rx/tx table, rx/tx masks must be identical */
> +	if (chan->qmc->is_tsa_64rxtx) {
> +		if (ts_info->rx_ts_mask != ts_info->tx_ts_mask)
> +			return -EINVAL;
> +	}
> +
> +	spin_lock_irqsave(&chan->ts_lock, flags);
> +
> +	if ((chan->tx_ts_mask != ts_info->tx_ts_mask && !chan->is_tx_stopped) ||
> +	    (chan->rx_ts_mask != ts_info->rx_ts_mask && !chan->is_rx_stopped)) {
> +		dev_err(chan->qmc->dev, "Channel rx and/or tx not stopped\n");
> +		ret = -EBUSY;
> +	} else {
> +		chan->tx_ts_mask = ts_info->tx_ts_mask;
> +		chan->rx_ts_mask = ts_info->rx_ts_mask;
> +		ret = 0;
> +	}
> +	spin_unlock_irqrestore(&chan->ts_lock, flags);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL(qmc_chan_set_ts_info);
> +
>   int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param)
>   {
>   	if (param->mode != chan->mode)
> diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
> index 6f1d6cebc9fe..802c161636bd 100644
> --- a/include/soc/fsl/qe/qmc.h
> +++ b/include/soc/fsl/qe/qmc.h
> @@ -38,6 +38,16 @@ struct qmc_chan_info {
>   
>   int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
>   
> +struct qmc_chan_ts_info {
> +	u64 rx_ts_mask_avail;
> +	u64 tx_ts_mask_avail;
> +	u64 rx_ts_mask;
> +	u64 tx_ts_mask;
> +};
> +
> +int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info);
> +int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info);
> +
>   struct qmc_chan_param {
>   	enum qmc_mode mode;
>   	union {
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Re: [PATCH v2 19/28] wan: qmc_hdlc: Add runtime timeslots changes support

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> QMC channels support runtime timeslots changes but nothing is done at
> the QMC HDLC driver to handle these changes.
> 
> Use existing IFACE ioctl in order to configure the timeslots to use.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/net/wan/fsl_qmc_hdlc.c | 169 ++++++++++++++++++++++++++++++++-
>   1 file changed, 168 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
> index b4ebae963d39..c449edf0a35e 100644
> --- a/drivers/net/wan/fsl_qmc_hdlc.c
> +++ b/drivers/net/wan/fsl_qmc_hdlc.c
> @@ -32,6 +32,7 @@ struct qmc_hdlc {
>   	struct qmc_hdlc_desc tx_descs[8];
>   	unsigned int tx_out;
>   	struct qmc_hdlc_desc rx_descs[4];
> +	u32 slot_map;
>   };
>   
>   static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
> @@ -202,6 +203,162 @@ static netdev_tx_t qmc_hdlc_xmit(struct sk_buff *skb, struct net_device *netdev)
>   	return NETDEV_TX_OK;
>   }
>   
> +static int qmc_hdlc_xlate_slot_map(struct qmc_hdlc *qmc_hdlc,
> +				   u32 slot_map, struct qmc_chan_ts_info *ts_info)
> +{
> +	u64 ts_mask_avail;
> +	unsigned int bit;
> +	unsigned int i;
> +	u64 ts_mask;
> +	u64 map = 0;
> +
> +	/* Tx and Rx masks must be identical */
> +	if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
> +		dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
> +			ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
> +		return -EINVAL;
> +	}
> +
> +	ts_mask_avail = ts_info->rx_ts_mask_avail;
> +	ts_mask = 0;
> +	map = slot_map;
> +	bit = 0;
> +	for (i = 0; i < 64; i++) {
> +		if (ts_mask_avail & BIT_ULL(i)) {
> +			if (map & BIT_ULL(bit))
> +				ts_mask |= BIT_ULL(i);
> +			bit++;
> +		}
> +	}
> +
> +	if (hweight64(ts_mask) != hweight64(map)) {
> +		dev_err(qmc_hdlc->dev, "Cannot translate timeslots 0x%llx -> (0x%llx,0x%llx)\n",
> +			map, ts_mask_avail, ts_mask);
> +		return -EINVAL;
> +	}
> +
> +	ts_info->tx_ts_mask = ts_mask;
> +	ts_info->rx_ts_mask = ts_mask;
> +	return 0;
> +}
> +
> +static int qmc_hdlc_xlate_ts_info(struct qmc_hdlc *qmc_hdlc,
> +				  const struct qmc_chan_ts_info *ts_info, u32 *slot_map)
> +{
> +	u64 ts_mask_avail;
> +	unsigned int bit;
> +	unsigned int i;
> +	u64 ts_mask;
> +	u64 map = 0;
> +
> +	/* Tx and Rx masks must be identical */
> +	if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
> +		dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
> +			ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
> +		return -EINVAL;
> +	}
> +	if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) {
> +		dev_err(qmc_hdlc->dev, "tx and rx timeslots mismatch (0x%llx, 0x%llx)\n",
> +			ts_info->rx_ts_mask, ts_info->tx_ts_mask);
> +		return -EINVAL;
> +	}
> +
> +	ts_mask_avail = ts_info->rx_ts_mask_avail;
> +	ts_mask = ts_info->rx_ts_mask;
> +	map = 0;
> +	bit = 0;
> +	for (i = 0; i < 64; i++) {
> +		if (ts_mask_avail & BIT_ULL(i)) {
> +			if (ts_mask & BIT_ULL(i))
> +				map |= BIT_ULL(bit);
> +			bit++;
> +		}
> +	}
> +
> +	if (hweight64(ts_mask) != hweight64(map)) {
> +		dev_err(qmc_hdlc->dev, "Cannot translate timeslots (0x%llx,0x%llx) -> 0x%llx\n",
> +			ts_mask_avail, ts_mask, map);
> +		return -EINVAL;
> +	}
> +
> +	if (map >= BIT_ULL(32)) {
> +		dev_err(qmc_hdlc->dev, "Slot map out of 32bit (0x%llx,0x%llx) -> 0x%llx\n",
> +			ts_mask_avail, ts_mask, map);
> +		return -EINVAL;
> +	}
> +
> +	*slot_map = map;
> +	return 0;
> +}
> +
> +static int qmc_hdlc_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface, const te1_settings *te1)
> +{
> +	struct qmc_chan_ts_info ts_info;
> +	int ret;
> +
> +	ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", ret);
> +		return ret;
> +	}
> +	ret = qmc_hdlc_xlate_slot_map(qmc_hdlc, te1->slot_map, &ts_info);
> +	if (ret)
> +		return ret;
> +
> +	ret = qmc_chan_set_ts_info(qmc_hdlc->qmc_chan, &ts_info);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "set QMC channel ts info failed %d\n", ret);
> +		return ret;
> +	}
> +
> +	qmc_hdlc->slot_map = te1->slot_map;
> +
> +	return 0;
> +}
> +
> +static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
> +{
> +	struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
> +	te1_settings te1;
> +
> +	switch (ifs->type) {
> +	case IF_GET_IFACE:
> +		ifs->type = IF_IFACE_E1;
> +		if (ifs->size < sizeof(te1)) {
> +			if (!ifs->size)
> +				return 0; /* only type requested */
> +
> +			ifs->size = sizeof(te1); /* data size wanted */
> +			return -ENOBUFS;
> +		}
> +
> +		memset(&te1, 0, sizeof(te1));
> +
> +		/* Update slot_map */
> +		te1.slot_map = qmc_hdlc->slot_map;
> +
> +		if (copy_to_user(ifs->ifs_ifsu.te1, &te1,  sizeof(te1)))
> +			return -EFAULT;
> +		return 0;
> +
> +	case IF_IFACE_E1:
> +	case IF_IFACE_T1:
> +		if (!capable(CAP_NET_ADMIN))
> +			return -EPERM;
> +
> +		if (netdev->flags & IFF_UP)
> +			return -EBUSY;
> +
> +		if (copy_from_user(&te1, ifs->ifs_ifsu.te1, sizeof(te1)))
> +			return -EFAULT;
> +
> +		return qmc_hdlc_set_iface(qmc_hdlc, ifs->type, &te1);
> +
> +	default:
> +		return hdlc_ioctl(netdev, ifs);
> +	}
> +}
> +
>   static int qmc_hdlc_open(struct net_device *netdev)
>   {
>   	struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
> @@ -328,13 +485,14 @@ static const struct net_device_ops qmc_hdlc_netdev_ops = {
>   	.ndo_open       = qmc_hdlc_open,
>   	.ndo_stop       = qmc_hdlc_close,
>   	.ndo_start_xmit = hdlc_start_xmit,
> -	.ndo_siocwandev	= hdlc_ioctl,
> +	.ndo_siocwandev = qmc_hdlc_ioctl,
>   };
>   
>   static int qmc_hdlc_probe(struct platform_device *pdev)
>   {
>   	struct device_node *np = pdev->dev.of_node;
>   	struct qmc_hdlc *qmc_hdlc;
> +	struct qmc_chan_ts_info ts_info;
>   	struct qmc_chan_info info;
>   	hdlc_device *hdlc;
>   	int ret;
> @@ -364,6 +522,15 @@ static int qmc_hdlc_probe(struct platform_device *pdev)
>   		return -EINVAL;
>   	}
>   
> +	ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", ret);
> +		return ret;
> +	}
> +	ret = qmc_hdlc_xlate_ts_info(qmc_hdlc, &ts_info, &qmc_hdlc->slot_map);
> +	if (ret)
> +		return ret;
> +
>   	qmc_hdlc->netdev = alloc_hdlcdev(qmc_hdlc);
>   	if (!qmc_hdlc->netdev) {
>   		dev_err(qmc_hdlc->dev, "failed to alloc hdlc dev\n");
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Re: [PATCH v2 20/28] net: wan: Add framer framework support

[Andrew Lunn]

> +int framer_pm_runtime_get(struct framer *framer)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return 0;

Can framer be a NULL pointer? This sort of test often covers up
bugs. So either let it dereference the NULL pointer and opps, or
return -EINVAL.

       Andrew

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Re: [PATCH v2 20/28] net: wan: Add framer framework support

[Herve Codina]

On Tue, 1 Aug 2023 11:56:12 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > +int framer_pm_runtime_get(struct framer *framer)
> > +{
> > +	int ret;
> > +
> > +	if (!framer)
> > +		return 0;  
> 
> Can framer be a NULL pointer? This sort of test often covers up
> bugs. So either let it dereference the NULL pointer and opps, or
> return -EINVAL.
> 

Well, in the current usage, it cannot be a NULL pointer.
I will simply remove the check (every where it is present) and
dereference the pointer instead of returning -EINVAL.

Regards,
Hervé

-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 20/28] net: wan: Add framer framework support

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> A framer is a component in charge of an E1/T1 line interface.
> Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
> frames. It also provides information related to the E1/T1 line.
> 
> The framer framework provides a set of APIs for the framer drivers
> (framer provider) to create/destroy a framer and APIs for the framer
> users (framer consumer) to obtain a reference to the framer, and
> use the framer.
> 
> This basic implementation provides a framer abstraction for:
>   - power on/off the framer
>   - get the framer status (line state)
>   - be notified on framer status changes
>   - get/set the framer configuration
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/net/wan/Kconfig                |   2 +
>   drivers/net/wan/Makefile               |   2 +
>   drivers/net/wan/framer/Kconfig         |  19 +
>   drivers/net/wan/framer/Makefile        |   6 +
>   drivers/net/wan/framer/framer-core.c   | 935 +++++++++++++++++++++++++
>   include/linux/framer/framer-provider.h | 194 +++++
>   include/linux/framer/framer.h          | 215 ++++++
>   7 files changed, 1373 insertions(+)
>   create mode 100644 drivers/net/wan/framer/Kconfig
>   create mode 100644 drivers/net/wan/framer/Makefile
>   create mode 100644 drivers/net/wan/framer/framer-core.c
>   create mode 100644 include/linux/framer/framer-provider.h
>   create mode 100644 include/linux/framer/framer.h
> 
> diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
> index 8de99f4b647b..31ab2136cdf1 100644
> --- a/drivers/net/wan/Kconfig
> +++ b/drivers/net/wan/Kconfig
> @@ -95,6 +95,8 @@ config HDLC_X25
>   comment "X.25/LAPB support is disabled"
>   	depends on HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
>   
> +source "drivers/net/wan/framer/Kconfig"
> +
>   config PCI200SYN
>   	tristate "Goramo PCI200SYN support"
>   	depends on HDLC && PCI
> diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
> index f338f4830626..00e9b7ee1e01 100644
> --- a/drivers/net/wan/Makefile
> +++ b/drivers/net/wan/Makefile
> @@ -14,6 +14,8 @@ obj-$(CONFIG_HDLC_FR)		+= hdlc_fr.o
>   obj-$(CONFIG_HDLC_PPP)		+= hdlc_ppp.o
>   obj-$(CONFIG_HDLC_X25)		+= hdlc_x25.o
>   
> +obj-y				+= framer/
> +
>   obj-$(CONFIG_FARSYNC)		+= farsync.o
>   
>   obj-$(CONFIG_LAPBETHER)		+= lapbether.o
> diff --git a/drivers/net/wan/framer/Kconfig b/drivers/net/wan/framer/Kconfig
> new file mode 100644
> index 000000000000..96ef1e7ba8eb
> --- /dev/null
> +++ b/drivers/net/wan/framer/Kconfig
> @@ -0,0 +1,19 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# FRAMER
> +#
> +
> +menu "Framer Subsystem"
> +
> +config GENERIC_FRAMER
> +	bool "Framer Core"
> +	help
> +	  Generic Framer support.
> +
> +	  This framework is designed to provide a generic interface for framer
> +	  devices present in the kernel. This layer will have the generic
> +	  API by which framer drivers can create framer using the framer
> +	  framework and framer users can obtain reference to the framer.
> +	  All the users of this framework should select this config.
> +
> +endmenu
> diff --git a/drivers/net/wan/framer/Makefile b/drivers/net/wan/framer/Makefile
> new file mode 100644
> index 000000000000..78dbd8e563d0
> --- /dev/null
> +++ b/drivers/net/wan/framer/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for the framer drivers.
> +#
> +
> +obj-$(CONFIG_GENERIC_FRAMER)			+= framer-core.o
> diff --git a/drivers/net/wan/framer/framer-core.c b/drivers/net/wan/framer/framer-core.c
> new file mode 100644
> index 000000000000..ef93b7d74fd1
> --- /dev/null
> +++ b/drivers/net/wan/framer/framer-core.c
> @@ -0,0 +1,935 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Generic Framer framework.
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/framer/framer.h>
> +#include <linux/framer/framer-provider.h>
> +#include <linux/idr.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +static struct class *framer_class;
> +static DEFINE_MUTEX(framer_provider_mutex);
> +static LIST_HEAD(framer_provider_list);
> +static DEFINE_IDA(framer_ida);
> +
> +#define dev_to_framer(a)	(container_of((a), struct framer, dev))
> +
> +int framer_pm_runtime_get(struct framer *framer)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return 0;
> +
> +	if (!pm_runtime_enabled(&framer->dev))
> +		return -EOPNOTSUPP;
> +
> +	ret = pm_runtime_get(&framer->dev);
> +	if (ret < 0 && ret != -EINPROGRESS)
> +		pm_runtime_put_noidle(&framer->dev);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_pm_runtime_get);
> +
> +int framer_pm_runtime_get_sync(struct framer *framer)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return 0;
> +
> +	if (!pm_runtime_enabled(&framer->dev))
> +		return -EOPNOTSUPP;
> +
> +	ret = pm_runtime_get_sync(&framer->dev);
> +	if (ret < 0)
> +		pm_runtime_put_sync(&framer->dev);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_pm_runtime_get_sync);
> +
> +int framer_pm_runtime_put(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	if (!pm_runtime_enabled(&framer->dev))
> +		return -EOPNOTSUPP;
> +
> +	return pm_runtime_put(&framer->dev);
> +}
> +EXPORT_SYMBOL_GPL(framer_pm_runtime_put);
> +
> +int framer_pm_runtime_put_sync(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	if (!pm_runtime_enabled(&framer->dev))
> +		return -EOPNOTSUPP;
> +
> +	return pm_runtime_put_sync(&framer->dev);
> +}
> +EXPORT_SYMBOL_GPL(framer_pm_runtime_put_sync);
> +
> +/**
> + * framer_init - framer internal initialization before framer operation
> + * @framer: the framer returned by framer_get()
> + *
> + * Used to allow framer's driver to perform framer internal initialization,
> + * such as PLL block powering, clock initialization or anything that's
> + * is required by the framer to perform the start of operation.
> + * Must be called before framer_power_on().
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_init(struct framer *framer)
> +{
> +	bool start_polling = false;
> +	int ret;
> +
> +	if (!framer)
> +		return 0;
> +
> +	ret = framer_pm_runtime_get_sync(framer);
> +	if (ret < 0 && ret != -EOPNOTSUPP)
> +		return ret;
> +	ret = 0; /* Override possible ret == -EOPNOTSUPP */
> +
> +	mutex_lock(&framer->mutex);
> +	if (framer->power_count > framer->init_count)
> +		dev_warn(&framer->dev, "framer_power_on was called before framer init\n");
> +
> +	if (framer->init_count == 0) {
> +		if (framer->ops->init) {
> +			ret = framer->ops->init(framer);
> +			if (ret < 0) {
> +				dev_err(&framer->dev, "framer init failed --> %d\n", ret);
> +				goto out;
> +			}
> +		}
> +		if (framer->ops->flags & FRAMER_FLAG_POLL_STATUS)
> +			start_polling = true;
> +	}
> +	++framer->init_count;
> +
> +out:
> +	mutex_unlock(&framer->mutex);
> +
> +	if (!ret && start_polling) {
> +		ret = framer_get_status(framer, &framer->prev_status);
> +		if (ret < 0) {
> +			dev_warn(&framer->dev, "framer get status failed --> %d\n", ret);
> +			/* Will be retried on polling_work */
> +			ret = 0;
> +		}
> +		queue_delayed_work(system_power_efficient_wq, &framer->polling_work, 1 * HZ);
> +	}
> +
> +	framer_pm_runtime_put(framer);
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_init);
> +
> +/**
> + * framer_exit - Framer internal un-initialization
> + * @framer: the framer returned by framer_get()
> + *
> + * Must be called after framer_power_off().
> + */
> +int framer_exit(struct framer *framer)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return 0;
> +
> +	ret = framer_pm_runtime_get_sync(framer);
> +	if (ret < 0 && ret != -EOPNOTSUPP)
> +		return ret;
> +	ret = 0; /* Override possible ret == -EOPNOTSUPP */
> +
> +	mutex_lock(&framer->mutex);
> +	--framer->init_count;
> +	if (framer->init_count == 0) {
> +		if (framer->ops->flags & FRAMER_FLAG_POLL_STATUS) {
> +			mutex_unlock(&framer->mutex);
> +			cancel_delayed_work_sync(&framer->polling_work);
> +			mutex_lock(&framer->mutex);
> +		}
> +
> +		if (framer->ops->exit)
> +			framer->ops->exit(framer);
> +	}
> +
> +	mutex_unlock(&framer->mutex);
> +	framer_pm_runtime_put(framer);
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_exit);
> +
> +/**
> + * framer_power_on - Enable the framer and enter proper operation
> + * @framer: the framer returned by framer_get()
> + *
> + * Must be called after framer_init().
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_power_on(struct framer *framer)
> +{
> +	int ret = 0;
> +
> +	if (!framer)
> +		goto out;
> +
> +	if (framer->pwr) {
> +		ret = regulator_enable(framer->pwr);
> +		if (ret)
> +			goto out;
> +	}
> +
> +	ret = framer_pm_runtime_get_sync(framer);
> +	if (ret < 0 && ret != -EOPNOTSUPP)
> +		goto err_pm_sync;
> +
> +	ret = 0; /* Override possible ret == -EOPNOTSUPP */
> +
> +	mutex_lock(&framer->mutex);
> +	if (framer->power_count == 0 && framer->ops->power_on) {
> +		ret = framer->ops->power_on(framer);
> +		if (ret < 0) {
> +			dev_err(&framer->dev, "framer poweron failed --> %d\n", ret);
> +			goto err_pwr_on;
> +		}
> +	}
> +	++framer->power_count;
> +	mutex_unlock(&framer->mutex);
> +	return 0;
> +
> +err_pwr_on:
> +	mutex_unlock(&framer->mutex);
> +	framer_pm_runtime_put_sync(framer);
> +err_pm_sync:
> +	if (framer->pwr)
> +		regulator_disable(framer->pwr);
> +out:
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_power_on);
> +
> +/**
> + * framer_power_off - Disable the framer.
> + * @framer: the framer returned by framer_get()
> + *
> + * Must be called before framer_exit().
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_power_off(struct framer *framer)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return 0;
> +
> +	mutex_lock(&framer->mutex);
> +	if (framer->power_count == 1 && framer->ops->power_off) {
> +		ret =  framer->ops->power_off(framer);
> +		if (ret < 0) {
> +			dev_err(&framer->dev, "framer poweroff failed --> %d\n", ret);
> +			mutex_unlock(&framer->mutex);
> +			return ret;
> +		}
> +	}
> +	--framer->power_count;
> +	mutex_unlock(&framer->mutex);
> +	framer_pm_runtime_put(framer);
> +
> +	if (framer->pwr)
> +		regulator_disable(framer->pwr);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(framer_power_off);
> +
> +/**
> + * framer_get_status() - Gets the framer status
> + * @framer: the framer returned by framer_get()
> + * @status: the status to retrieve
> + *
> + * Used to get the framer status. framer_init() must have been called
> + * on the framer.
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_get_status(struct framer *framer, struct framer_status *status)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return -EINVAL;
> +
> +	if (!framer->ops->get_status)
> +		return -EOPNOTSUPP;
> +
> +	/* Be sure to have known values (struct padding and future extensions) */
> +	memset(status, 0, sizeof(*status));
> +
> +	mutex_lock(&framer->mutex);
> +	ret = framer->ops->get_status(framer, status);
> +	mutex_unlock(&framer->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_get_status);
> +
> +/**
> + * framer_set_config() - Sets the framer configuration
> + * @framer: the framer returned by framer_get()
> + * @config: the configuration to set
> + *
> + * Used to set the framer configuration. framer_init() must have been called
> + * on the framer.
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_set_config(struct framer *framer, const struct framer_config *config)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return -EINVAL;
> +
> +	if (!framer->ops->set_config)
> +		return -EOPNOTSUPP;
> +
> +	mutex_lock(&framer->mutex);
> +	ret = framer->ops->set_config(framer, config);
> +	mutex_unlock(&framer->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_set_config);
> +
> +/**
> + * framer_get_config() - Gets the framer configuration
> + * @framer: the framer returned by framer_get()
> + * @config: the configuration to retrieve
> + *
> + * Used to get the framer configuration. framer_init() must have been called
> + * on the framer.
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_get_config(struct framer *framer, struct framer_config *config)
> +{
> +	int ret;
> +
> +	if (!framer)
> +		return -EINVAL;
> +
> +	if (!framer->ops->get_config)
> +		return -EOPNOTSUPP;
> +
> +	mutex_lock(&framer->mutex);
> +	ret = framer->ops->get_config(framer, config);
> +	mutex_unlock(&framer->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(framer_get_config);
> +
> +static void framer_polling_work(struct work_struct *work)
> +{
> +	struct framer *framer = container_of(work, struct framer, polling_work.work);
> +	struct framer_status status;
> +	int ret;
> +
> +	ret = framer_get_status(framer, &status);
> +	if (ret) {
> +		dev_err(&framer->dev, "polling, get status failed (%d)\n", ret);
> +		goto end;
> +	}
> +	if (memcmp(&framer->prev_status, &status, sizeof(status))) {
> +		blocking_notifier_call_chain(&framer->notifier_list,
> +					     FRAMER_EVENT_STATUS, NULL);
> +		memcpy(&framer->prev_status, &status, sizeof(status));
> +	}
> +
> +end:
> +	/* Re-schedule task in 1 sec */
> +	queue_delayed_work(system_power_efficient_wq, &framer->polling_work, 1 * HZ);
> +}
> +
> +/**
> + * framer_notifier_register() - Registers a notifier
> + * @framer: the framer returned by framer_get()
> + * @nb: the notifier block to register
> + *
> + * Used to register a notifier block on framer events. framer_init() must have
> + * been called on the framer.
> + * The available framer events are present in enum framer_events.
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_notifier_register(struct framer *framer, struct notifier_block *nb)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	return blocking_notifier_chain_register(&framer->notifier_list, nb);
> +}
> +EXPORT_SYMBOL_GPL(framer_notifier_register);
> +
> +/**
> + * framer_notifier_unregister() - Unregisters a notifier
> + * @framer: the framer returned by framer_get()
> + * @nb: the notifier block to unregister
> + *
> + * Used to unregister a notifier block. framer_init() must have
> + * been called on the framer.
> + *
> + * Return: %0 if successful, a negative error code otherwise
> + */
> +int framer_notifier_unregister(struct framer *framer, struct notifier_block *nb)
> +{
> +	if (!framer)
> +		return -EINVAL;
> +
> +	return blocking_notifier_chain_unregister(&framer->notifier_list, nb);
> +}
> +EXPORT_SYMBOL_GPL(framer_atomic_notifier_unregister);
> +
> +static struct framer_provider *framer_provider_of_lookup(const struct device_node *node)
> +{
> +	struct framer_provider *framer_provider;
> +
> +	list_for_each_entry(framer_provider, &framer_provider_list, list) {
> +		if (device_match_of_node(framer_provider->dev, node))
> +			return framer_provider;
> +	}
> +
> +	return ERR_PTR(-EPROBE_DEFER);
> +}
> +
> +static struct framer *framer_of_get_from_provider(struct of_phandle_args *args)
> +{
> +	struct framer_provider *framer_provider;
> +	struct framer *framer;
> +
> +	mutex_lock(&framer_provider_mutex);
> +	framer_provider = framer_provider_of_lookup(args->np);
> +	if (IS_ERR(framer_provider) || !try_module_get(framer_provider->owner)) {
> +		framer = ERR_PTR(-EPROBE_DEFER);
> +		goto end;
> +	}
> +
> +	framer = framer_provider->of_xlate(framer_provider->dev, args);
> +
> +	module_put(framer_provider->owner);
> +
> +end:
> +	mutex_unlock(&framer_provider_mutex);
> +
> +	return framer;
> +}
> +
> +static struct framer *framer_of_get_byphandle(struct device_node *np, const char *propname,
> +					      int index)
> +{
> +	struct of_phandle_args args;
> +	struct framer *framer;
> +	int ret;
> +
> +	ret = of_parse_phandle_with_args(np, propname, "#framer-cells", index, &args);
> +	if (ret)
> +		return ERR_PTR(-ENODEV);
> +
> +	if (!of_device_is_available(args.np)) {
> +		framer = ERR_PTR(-ENODEV);
> +		goto out_node_put;
> +	}
> +
> +	framer = framer_of_get_from_provider(&args);
> +
> +out_node_put:
> +	of_node_put(args.np);
> +
> +	return framer;
> +}
> +
> +static struct framer *framer_of_get_byparent(struct device_node *np, int index)
> +{
> +	struct of_phandle_args args;
> +	struct framer *framer;
> +
> +	args.np = of_get_parent(np);
> +	args.args_count = 1;
> +	args.args[0] = index;
> +
> +	while (args.np) {
> +		framer = framer_of_get_from_provider(&args);
> +		if (IS_ERR(framer) && PTR_ERR(framer) != -EPROBE_DEFER) {
> +			args.np = of_get_next_parent(args.np);
> +			continue;
> +		}
> +		of_node_put(args.np);
> +		return framer;
> +	}
> +
> +	return ERR_PTR(-ENODEV);
> +}
> +
> +/**
> + * framer_get() - lookup and obtain a reference to a framer.
> + * @dev: device that requests the framer
> + * @con_id: name of the framer from device's point of view
> + *
> + * Returns the framer driver, after getting a refcount to it; or
> + * -ENODEV if there is no such framer. The caller is responsible for
> + * calling framer_put() to release that count.
> + */
> +struct framer *framer_get(struct device *dev, const char *con_id)
> +{
> +	struct framer *framer = ERR_PTR(-ENODEV);
> +	struct device_link *link;
> +	int ret;
> +
> +	if (dev->of_node) {
> +		if (con_id)
> +			framer = framer_of_get_byphandle(dev->of_node, con_id, 0);
> +		else
> +			framer = framer_of_get_byparent(dev->of_node, 0);
> +	}
> +
> +	if (IS_ERR(framer))
> +		return framer;
> +
> +	get_device(&framer->dev);
> +
> +	if (!try_module_get(framer->ops->owner)) {
> +		ret = -EPROBE_DEFER;
> +		goto err_put_device;
> +	}
> +
> +	link = device_link_add(dev, &framer->dev, DL_FLAG_STATELESS);
> +	if (!link) {
> +		dev_err(dev, "failed to create device_link to %s\n", dev_name(&framer->dev));
> +		ret = -EPROBE_DEFER;
> +		goto err_module_put;
> +	}
> +
> +	return framer;
> +
> +err_module_put:
> +	module_put(framer->ops->owner);
> +err_put_device:
> +	put_device(&framer->dev);
> +	return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(framer_get);
> +
> +/**
> + * framer_put() - release the framer
> + * @dev: device that wants to release this framer
> + * @framer: the framer returned by framer_get()
> + *
> + * Releases a refcount the caller received from framer_get().
> + */
> +void framer_put(struct device *dev, struct framer *framer)
> +{
> +	if (!framer || IS_ERR(framer))
> +		return;
> +
> +	device_link_remove(dev, &framer->dev);
> +
> +	module_put(framer->ops->owner);
> +	put_device(&framer->dev);
> +}
> +EXPORT_SYMBOL_GPL(framer_put);
> +
> +static void devm_framer_put(struct device *dev, void *res)
> +{
> +	struct framer *framer = *(struct framer **)res;
> +
> +	framer_put(dev, framer);
> +}
> +
> +/**
> + * devm_framer_get() - lookup and obtain a reference to a framer.
> + * @dev: device that requests this framer
> + * @con_id: name of the framer from device's point of view
> + *
> + * Gets the framer using framer_get(), and associates a device with it using
> + * devres. On driver detach, framer_put() function is invoked on the devres
> + * data, then, devres data is freed.
> + */
> +struct framer *devm_framer_get(struct device *dev, const char *con_id)
> +{
> +	struct framer **ptr, *framer;
> +
> +	ptr = devres_alloc(devm_framer_put, sizeof(*ptr), GFP_KERNEL);
> +	if (!ptr)
> +		return ERR_PTR(-ENOMEM);
> +
> +	framer = framer_get(dev, con_id);
> +	if (!IS_ERR(framer)) {
> +		*ptr = framer;
> +		devres_add(dev, ptr);
> +	} else {
> +		devres_free(ptr);
> +		return framer;
> +	}
> +
> +	return framer;
> +}
> +EXPORT_SYMBOL_GPL(devm_framer_get);
> +
> +/**
> + * devm_framer_optional_get() - lookup and obtain a reference to an optional
> + * framer.
> + * @dev: device that requests this framer
> + * @con_id: name of the framer from device's point of view
> + *
> + * Same as devm_framer_get() except that if the framer does not exist, it is not
> + * considered an error and -ENODEV will not be returned. Instead the NULL framer
> + * is returned, which can be passed to other framer consumer calls.
> + */
> +struct framer *devm_framer_optional_get(struct device *dev, const char *con_id)
> +{
> +	struct framer *framer = devm_framer_get(dev, con_id);
> +
> +	if (PTR_ERR(framer) == -ENODEV)
> +		framer = NULL;
> +
> +	return framer;
> +}
> +EXPORT_SYMBOL_GPL(devm_framer_optional_get);
> +
> +static void framer_notify_status_work(struct work_struct *work)
> +{
> +	struct framer *framer = container_of(work, struct framer, notify_status_work);
> +
> +	blocking_notifier_call_chain(&framer->notifier_list, FRAMER_EVENT_STATUS, NULL);
> +}
> +
> +void framer_notify_status_change(struct framer *framer)
> +{
> +	if (!framer)
> +		return;
> +
> +	/* Can be called from atomic context -> just schedule a task to call
> +	 * blocking notifiers
> +	 */
> +	queue_work(system_power_efficient_wq, &framer->notify_status_work);
> +}
> +EXPORT_SYMBOL_GPL(framer_notify_status_change);
> +
> +/**
> + * framer_create() - create a new framer
> + * @dev: device that is creating the new framer
> + * @node: device node of the framer. default to dev->of_node.
> + * @ops: function pointers for performing framer operations
> + *
> + * Called to create a framer using framer framework.
> + */
> +struct framer *framer_create(struct device *dev, struct device_node *node,
> +			     const struct framer_ops *ops)
> +{
> +	int ret;
> +	int id;
> +	struct framer *framer;
> +
> +	if (WARN_ON(!dev))
> +		return ERR_PTR(-EINVAL);
> +
> +	/* get_status() is mandatory if the provider ask for polling status */
> +	if (WARN_ON((ops->flags & FRAMER_FLAG_POLL_STATUS) && !ops->get_status))
> +		return ERR_PTR(-EINVAL);
> +
> +	framer = kzalloc(sizeof(*framer), GFP_KERNEL);
> +	if (!framer)
> +		return ERR_PTR(-ENOMEM);
> +
> +	id = ida_simple_get(&framer_ida, 0, 0, GFP_KERNEL);
> +	if (id < 0) {
> +		dev_err(dev, "unable to get id\n");
> +		ret = id;
> +		goto free_framer;
> +	}
> +
> +	device_initialize(&framer->dev);
> +	mutex_init(&framer->mutex);
> +	INIT_WORK(&framer->notify_status_work, framer_notify_status_work);
> +	INIT_DELAYED_WORK(&framer->polling_work, framer_polling_work);
> +	BLOCKING_INIT_NOTIFIER_HEAD(&framer->notifier_list);
> +
> +	framer->dev.class = framer_class;
> +	framer->dev.parent = dev;
> +	framer->dev.of_node = node ? node : dev->of_node;
> +	framer->id = id;
> +	framer->ops = ops;
> +
> +	ret = dev_set_name(&framer->dev, "framer-%s.%d", dev_name(dev), id);
> +	if (ret)
> +		goto put_dev;
> +
> +	/* framer-supply */
> +	framer->pwr = regulator_get_optional(&framer->dev, "framer");
> +	if (IS_ERR(framer->pwr)) {
> +		ret = PTR_ERR(framer->pwr);
> +		if (ret == -EPROBE_DEFER)
> +			goto put_dev;
> +
> +		framer->pwr = NULL;
> +	}
> +
> +	ret = device_add(&framer->dev);
> +	if (ret)
> +		goto put_dev;
> +
> +	if (pm_runtime_enabled(dev)) {
> +		pm_runtime_enable(&framer->dev);
> +		pm_runtime_no_callbacks(&framer->dev);
> +	}
> +
> +	return framer;
> +
> +put_dev:
> +	put_device(&framer->dev);  /* calls framer_release() which frees resources */
> +	return ERR_PTR(ret);
> +
> +free_framer:
> +	kfree(framer);
> +	return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(framer_create);
> +
> +/**
> + * framer_destroy() - destroy the framer
> + * @framer: the framer to be destroyed
> + *
> + * Called to destroy the framer.
> + */
> +void framer_destroy(struct framer *framer)
> +{
> +	/* polling_work should already be stopped but if framer_exit() was not
> +	 * called (bug), here it's the last time to do that ...
> +	 */
> +	cancel_delayed_work_sync(&framer->polling_work);
> +	cancel_work_sync(&framer->notify_status_work);
> +	pm_runtime_disable(&framer->dev);
> +	device_unregister(&framer->dev); /* calls framer_release() which frees resources */
> +}
> +EXPORT_SYMBOL_GPL(framer_destroy);
> +
> +static void devm_framer_destroy(struct device *dev, void *res)
> +{
> +	struct framer *framer = *(struct framer **)res;
> +
> +	framer_destroy(framer);
> +}
> +
> +/**
> + * devm_framer_create() - create a new framer
> + * @dev: device that is creating the new framer
> + * @node: device node of the framer
> + * @ops: function pointers for performing framer operations
> + *
> + * Creates a new framer device adding it to the framer class.
> + * While at that, it also associates the device with the framer using devres.
> + * On driver detach, release function is invoked on the devres data,
> + * then, devres data is freed.
> + */
> +struct framer *devm_framer_create(struct device *dev, struct device_node *node,
> +				  const struct framer_ops *ops)
> +{
> +	struct framer **ptr, *framer;
> +
> +	ptr = devres_alloc(devm_framer_destroy, sizeof(*ptr), GFP_KERNEL);
> +	if (!ptr)
> +		return ERR_PTR(-ENOMEM);
> +
> +	framer = framer_create(dev, node, ops);
> +	if (!IS_ERR(framer)) {
> +		*ptr = framer;
> +		devres_add(dev, ptr);
> +	} else {
> +		devres_free(ptr);
> +	}
> +
> +	return framer;
> +}
> +EXPORT_SYMBOL_GPL(devm_framer_create);
> +
> +/**
> + * framer_provider_simple_of_xlate() - returns the framer instance from framer provider
> + * @dev: the framer provider device
> + * @args: of_phandle_args (not used here)
> + *
> + * Intended to be used by framer provider for the common case where #framer-cells is
> + * 0. For other cases where #framer-cells is greater than '0', the framer provider
> + * should provide a custom of_xlate function that reads the *args* and returns
> + * the appropriate framer.
> + */
> +struct framer *framer_provider_simple_of_xlate(struct device *dev, struct of_phandle_args *args)
> +{
> +	struct framer *framer;
> +	struct class_dev_iter iter;
> +
> +	class_dev_iter_init(&iter, framer_class, NULL, NULL);
> +	while ((dev = class_dev_iter_next(&iter))) {
> +		framer = dev_to_framer(dev);
> +		if (args->np != framer->dev.of_node)
> +			continue;
> +
> +		class_dev_iter_exit(&iter);
> +		return framer;
> +	}
> +
> +	class_dev_iter_exit(&iter);
> +	return ERR_PTR(-ENODEV);
> +}
> +EXPORT_SYMBOL_GPL(framer_simple_of_xlate);
> +
> +/**
> + * __framer_provider_of_register() - create/register framer provider with the framework
> + * @dev: struct device of the framer provider
> + * @owner: the module owner containing of_xlate
> + * @of_xlate: function pointer to obtain framer instance from framer provider
> + *
> + * Creates struct framer_provider from dev and of_xlate function pointer.
> + * This is used in the case of dt boot for finding the framer instance from
> + * framer provider.
> + */
> +struct framer_provider *
> +__framer_provider_of_register(struct device *dev, struct module *owner,
> +			      struct framer *(*of_xlate)(struct device *dev,
> +							 struct of_phandle_args *args))
> +{
> +	struct framer_provider *framer_provider;
> +
> +	framer_provider = kzalloc(sizeof(*framer_provider), GFP_KERNEL);
> +	if (!framer_provider)
> +		return ERR_PTR(-ENOMEM);
> +
> +	framer_provider->dev = dev;
> +	framer_provider->owner = owner;
> +	framer_provider->of_xlate = of_xlate;
> +
> +	of_node_get(framer_provider->dev->of_node);
> +
> +	mutex_lock(&framer_provider_mutex);
> +	list_add_tail(&framer_provider->list, &framer_provider_list);
> +	mutex_unlock(&framer_provider_mutex);
> +
> +	return framer_provider;
> +}
> +EXPORT_SYMBOL_GPL(__framer_provider_of_register);
> +
> +/**
> + * framer_provider_of_unregister() - unregister framer provider from the framework
> + * @framer_provider: framer provider returned by framer_provider_of_register()
> + *
> + * Removes the framer_provider created using framer_provider_of_register().
> + */
> +void framer_provider_of_unregister(struct framer_provider *framer_provider)
> +{
> +	if (IS_ERR(framer_provider))
> +		return;
> +
> +	mutex_lock(&framer_provider_mutex);
> +	list_del(&framer_provider->list);
> +	of_node_put(framer_provider->dev->of_node);
> +	kfree(framer_provider);
> +	mutex_unlock(&framer_provider_mutex);
> +}
> +EXPORT_SYMBOL_GPL(of_framer_provider_unregister);
> +
> +static void devm_framer_provider_of_unregister(struct device *dev, void *res)
> +{
> +	struct framer_provider *framer_provider = *(struct framer_provider **)res;
> +
> +	framer_provider_of_unregister(framer_provider);
> +}
> +
> +/**
> + * __devm_framer_provider_of_register() - create/register framer provider with
> + * the framework
> + * @dev: struct device of the framer provider
> + * @owner: the module owner containing of_xlate
> + * @of_xlate: function pointer to obtain framer instance from framer provider
> + *
> + * Creates struct framer_provider from dev and of_xlate function pointer.
> + * This is used in the case of dt boot for finding the framer instance from
> + * framer provider. While at that, it also associates the device with the
> + * framer provider using devres. On driver detach, release function is invoked
> + * on the devres data, then, devres data is freed.
> + */
> +struct framer_provider *
> +__devm_framer_provider_of_register(struct device *dev, struct module *owner,
> +				   struct framer *(*of_xlate)(struct device *dev,
> +							      struct of_phandle_args *args))
> +{
> +	struct framer_provider **ptr, *framer_provider;
> +
> +	ptr = devres_alloc(devm_framer_provider_of_unregister, sizeof(*ptr), GFP_KERNEL);
> +	if (!ptr)
> +		return ERR_PTR(-ENOMEM);
> +
> +	framer_provider = __framer_provider_of_register(dev, owner, of_xlate);
> +	if (!IS_ERR(framer_provider)) {
> +		*ptr = framer_provider;
> +		devres_add(dev, ptr);
> +	} else {
> +		devres_free(ptr);
> +	}
> +
> +	return framer_provider;
> +}
> +EXPORT_SYMBOL_GPL(__devm_framer_provider_of_register);
> +
> +/**
> + * framer_release() - release the framer
> + * @dev: the dev member within framer
> + *
> + * When the last reference to the device is removed, it is called
> + * from the embedded kobject as release method.
> + */
> +static void framer_release(struct device *dev)
> +{
> +	struct framer *framer;
> +
> +	framer = dev_to_framer(dev);
> +	regulator_put(framer->pwr);
> +	ida_simple_remove(&framer_ida, framer->id);
> +	kfree(framer);
> +}
> +
> +static int __init framer_core_init(void)
> +{
> +	framer_class = class_create("framer");
> +	if (IS_ERR(framer_class)) {
> +		pr_err("failed to create framer class (%pe)\n", framer_class);
> +		return PTR_ERR(framer_class);
> +	}
> +
> +	framer_class->dev_release = framer_release;
> +
> +	return 0;
> +}
> +device_initcall(framer_core_init);
> diff --git a/include/linux/framer/framer-provider.h b/include/linux/framer/framer-provider.h
> new file mode 100644
> index 000000000000..941a343c3ba7
> --- /dev/null
> +++ b/include/linux/framer/framer-provider.h
> @@ -0,0 +1,194 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Generic framer profider header file
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#ifndef __DRIVERS_PROVIDER_FRAMER_H
> +#define __DRIVERS_PROVIDER_FRAMER_H
> +
> +#include <linux/export.h>
> +#include <linux/framer/framer.h>
> +#include <linux/types.h>
> +
> +#define FRAMER_FLAG_POLL_STATUS  BIT(0)
> +
> +/**
> + * struct framer_ops - set of function pointers for performing framer operations
> + * @init: operation to be performed for initializing the framer
> + * @exit: operation to be performed while exiting
> + * @power_on: powering on the framer
> + * @power_off: powering off the framer
> + * @flags: OR-ed flags (FRAMER_FLAG_*) to ask for core functionality
> + *          - @FRAMER_FLAG_POLL_STATUS:
> + *            Ask the core to perfom a polling to get the framer status and
> + *            notify consumers on change.
> + *            The framer should call @framer_notify_status_change() when it
> + *            detects a status change. This is usally done using interrutps.
> + *            If the framer cannot detect this change, it can ask the core for
> + *            a status polling. The core will call @get_status() periodically
> + *            and, on change detected, it will notify the consumer.
> + *            the @get_status()
> + * @owner: the module owner containing the ops
> + */
> +struct framer_ops {
> +	int	(*init)(struct framer *framer);
> +	void	(*exit)(struct framer *framer);
> +	int	(*power_on)(struct framer *framer);
> +	int	(*power_off)(struct framer *framer);
> +
> +	/**
> +	 * @get_status:
> +	 *
> +	 * Optional.
> +	 *
> +	 * Used to get the framer status. framer_init() must have
> +	 * been called on the framer.
> +	 *
> +	 * Returns: 0 if successful, an negative error code otherwise
> +	 */
> +	int	(*get_status)(struct framer *framer, struct framer_status *status);
> +
> +	/**
> +	 * @set_config:
> +	 *
> +	 * Optional.
> +	 *
> +	 * Used to set the framer configuration. framer_init() must have
> +	 * been called on the framer.
> +	 *
> +	 * Returns: 0 if successful, an negative error code otherwise
> +	 */
> +	int	(*set_config)(struct framer *framer, const struct framer_config *config);
> +
> +	/**
> +	 * @get_config:
> +	 *
> +	 * Optional.
> +	 *
> +	 * Used to get the framer configuration. framer_init() must have
> +	 * been called on the framer.
> +	 *
> +	 * Returns: 0 if successful, an negative error code otherwise
> +	 */
> +	int	(*get_config)(struct framer *framer, struct framer_config *config);
> +
> +	u32 flags;
> +	struct module *owner;
> +};
> +
> +/**
> + * struct framer_provider - represents the framer provider
> + * @dev: framer provider device
> + * @children: can be used to override the default (dev->of_node) child node
> + * @owner: the module owner having of_xlate
> + * @list: to maintain a linked list of framer providers
> + * @of_xlate: function pointer to obtain framer instance from framer pointer
> + */
> +struct framer_provider {
> +	struct device		*dev;
> +	struct module		*owner;
> +	struct list_head	list;
> +	struct framer * (*of_xlate)(struct device *dev,
> +				    struct of_phandle_args *args);
> +};
> +
> +static inline void framer_set_drvdata(struct framer *framer, void *data)
> +{
> +	dev_set_drvdata(&framer->dev, data);
> +}
> +
> +static inline void *framer_get_drvdata(struct framer *framer)
> +{
> +	return dev_get_drvdata(&framer->dev);
> +}
> +
> +#if IS_ENABLED(CONFIG_GENERIC_FRAMER)
> +
> +/* Create and destroy a framer */
> +struct framer *framer_create(struct device *dev, struct device_node *node,
> +			     const struct framer_ops *ops);
> +void framer_destroy(struct framer *framer);
> +
> +/* devm version */
> +struct framer *devm_framer_create(struct device *dev, struct device_node *node,
> +				  const struct framer_ops *ops);
> +
> +struct framer *framer_provider_simple_of_xlate(struct device *dev,
> +					       struct of_phandle_args *args);
> +
> +struct framer_provider *
> +__framer_provider_of_register(struct device *dev, struct module *owner,
> +			      struct framer *(*of_xlate)(struct device *dev,
> +							 struct of_phandle_args *args));
> +
> +void framer_provider_of_unregister(struct framer_provider *framer_provider);
> +
> +struct framer_provider *
> +__devm_framer_provider_of_register(struct device *dev, struct module *owner,
> +				   struct framer *(*of_xlate)(struct device *dev,
> +							      struct of_phandle_args *args));
> +
> +void framer_notify_status_change(struct framer *framer);
> +
> +#else /* IS_ENABLED(CONFIG_GENERIC_FRAMER) */
> +
> +static inline struct framer *framer_create(struct device *dev, struct device_node *node,
> +					   const struct framer_ops *ops)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline void framer_destroy(struct framer *framer)
> +{
> +}
> +
> +/* devm version */
> +static inline struct framer *devm_framer_create(struct device *dev, struct device_node *node,
> +						const struct framer_ops *ops)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline struct framer *framer_provider_simple_of_xlate(struct device *dev,
> +							     struct of_phandle_args *args)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline struct framer_provider *
> +__framer_provider_of_register(struct device *dev, struct module *owner,
> +			      struct framer *(*of_xlate)(struct device *dev,
> +							 struct of_phandle_args *args))
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +void framer_provider_of_unregister(struct framer_provider *framer_provider)
> +{
> +}
> +
> +static inline struct framer_provider *
> +__devm_framer_provider_of_register(struct device *dev, struct module *owner,
> +				   struct framer *(*of_xlate)(struct device *dev,
> +							      struct of_phandle_args *args))
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +void framer_notify_status_change(struct framer *framer)
> +{
> +}
> +
> +#endif /* IS_ENABLED(CONFIG_GENERIC_FRAMER) */
> +
> +#define framer_provider_of_register(dev, xlate)		\
> +	__framer_provider_of_register((dev), THIS_MODULE, (xlate))
> +
> +#define devm_framer_provider_of_register(dev, xlate)	\
> +	__devm_framer_provider_of_register((dev), THIS_MODULE, (xlate))
> +
> +#endif /* __DRIVERS_PROVIDER_FRAMER_H */
> diff --git a/include/linux/framer/framer.h b/include/linux/framer/framer.h
> new file mode 100644
> index 000000000000..b735027f6801
> --- /dev/null
> +++ b/include/linux/framer/framer.h
> @@ -0,0 +1,215 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Generic framer header file
> + *
> + * Copyright 2023 CS GROUP France
> + *
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#ifndef __DRIVERS_FRAMER_H
> +#define __DRIVERS_FRAMER_H
> +
> +#include <linux/err.h>
> +#include <linux/mutex.h>
> +#include <linux/notifier.h>
> +#include <linux/of.h>
> +#include <linux/device.h>
> +#include <linux/workqueue.h>
> +
> +/**
> + * enum framer_iface - Framer interface
> + */
> +enum framer_iface {
> +	FRAMER_IFACE_E1,      /* E1 interface */
> +	FRAMER_IFACE_T1,      /* T1 interface */
> +};
> +
> +/**
> + * enum framer_clock_mode - Framer clock mode
> + */
> +enum framer_clock_type {
> +	FRAMER_CLOCK_EXT, /* External clock */
> +	FRAMER_CLOCK_INT, /* Internal clock */
> +};
> +
> +/**
> + * struct framer_configuration - Framer configuration
> + * @line_iface: Framer line interface
> + * @clock_mode: Framer clock type
> + * @clock_rate: Framer clock rate
> + */
> +struct framer_config {
> +	enum framer_iface iface;
> +	enum framer_clock_type clock_type;
> +	unsigned long line_clock_rate;
> +};
> +
> +/**
> + * struct framer_status - Framer status
> + * @link_is_on: Framer link state. true, the link is on, false, the link is off.
> + */
> +struct framer_status {
> +	bool link_is_on;
> +};
> +
> +/**
> + * framer_event - event available for notification
> + */
> +enum framer_event {
> +	FRAMER_EVENT_STATUS,	/* Event notified on framer_status changes */
> +};
> +
> +/**
> + * struct framer - represents the framer device
> + * @dev: framer device
> + * @id: id of the framer device
> + * @ops: function pointers for performing framer operations
> + * @mutex: mutex to protect framer_ops
> + * @init_count: used to protect when the framer is used by multiple consumers
> + * @power_count: used to protect when the framer is used by multiple consumers
> + * @pwr: power regulator associated with the framer
> + * @polling_task: polling task used if framer notifier operations are not provided
> + * @polling_notifier_list: notifier list used by the polling task
> + * @prev_status: previous read status used by the polling task to detect changes
> + */
> +struct framer {
> +	struct device			dev;
> +	int				id;
> +	const struct framer_ops		*ops;
> +	struct mutex			mutex;	/* Protect framer */
> +	int				init_count;
> +	int				power_count;
> +	struct regulator		*pwr;
> +	struct work_struct		notify_status_work;
> +	struct blocking_notifier_head	notifier_list;
> +	struct delayed_work		polling_work;
> +	struct framer_status		prev_status;
> +};
> +
> +#if IS_ENABLED(CONFIG_GENERIC_FRAMER)
> +int framer_pm_runtime_get(struct framer *framer);
> +int framer_pm_runtime_get_sync(struct framer *framer);
> +int framer_pm_runtime_put(struct framer *framer);
> +int framer_pm_runtime_put_sync(struct framer *framer);
> +int framer_init(struct framer *framer);
> +int framer_exit(struct framer *framer);
> +int framer_power_on(struct framer *framer);
> +int framer_power_off(struct framer *framer);
> +int framer_get_status(struct framer *framer, struct framer_status *status);
> +int framer_get_config(struct framer *framer, struct framer_config *config);
> +int framer_set_config(struct framer *framer, const struct framer_config *config);
> +int framer_notifier_register(struct framer *framer, struct notifier_block *nb);
> +int framer_notifier_unregister(struct framer *framer, struct notifier_block *nb);
> +
> +struct framer *framer_get(struct device *dev, const char *con_id);
> +void framer_put(struct device *dev, struct framer *framer);
> +
> +struct framer *devm_framer_get(struct device *dev, const char *con_id);
> +struct framer *devm_framer_optional_get(struct device *dev, const char *con_id);
> +#else
> +static inline int framer_pm_runtime_get(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_pm_runtime_get_sync(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_pm_runtime_put(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_pm_runtime_put_sync(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_init(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_exit(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_power_on(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_power_off(struct framer *framer)
> +{
> +	if (!framer)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_get_status(struct framer *framer, struct framer_status *status)
> +{
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_get_config(struct framer *framer, struct framer_config *config)
> +{
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_set_config(struct framer *framer, const struct framer_config *config)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_notifier_register(struct framer *framer,
> +					   struct notifier_block *nb)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	return -ENOSYS;
> +}
> +
> +static inline int framer_notifier_unregister(struct framer *framer,
> +					     struct notifier_block *nb)
> +{
> +	if (!framer)
> +		return 0;
> +
> +	return -ENOSYS;
> +}
> +
> +static inline struct framer *devm_framer_get(struct device *dev, const char *con_id)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +static inline struct framer *devm_framer_optional_get(struct device *dev, const char *con_id)
> +{
> +	return NULL;
> +}
> +
> +#endif
> +
> +#endif /* __DRIVERS_FRAMER_H */
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Re: [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting

[Lee Jones]

On Wed, 26 Jul 2023, Herve Codina wrote:

> The loop searching for a matching device based on its compatible
> string is aborted when a matching disabled device is found.
> This abort avoid to add devices as soon as one disabled device
> is found.
> 
> Continue searching for an other device instead of aborting on the
> first disabled one fixes the issue.
> 
> Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored without error")
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  drivers/mfd/mfd-core.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
> index 0ed7c0d7784e..bcc26e64639a 100644
> --- a/drivers/mfd/mfd-core.c
> +++ b/drivers/mfd/mfd-core.c
> @@ -146,6 +146,7 @@ static int mfd_add_device(struct device *parent, int id,
>  	struct platform_device *pdev;
>  	struct device_node *np = NULL;
>  	struct mfd_of_node_entry *of_entry, *tmp;
> +	bool disabled;
>  	int ret = -ENOMEM;
>  	int platform_id;
>  	int r;
> @@ -181,13 +182,13 @@ static int mfd_add_device(struct device *parent, int id,
>  		goto fail_res;
>  
>  	if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
> +		disabled = false;

This does not appear to reside in a loop.

Why not set it to false on declaration?

>  		for_each_child_of_node(parent->of_node, np) {
>  			if (of_device_is_compatible(np, cell->of_compatible)) {
> -				/* Ignore 'disabled' devices error free */
> +				/* Skip 'disabled' devices */
>  				if (!of_device_is_available(np)) {
> -					of_node_put(np);

Doesn't this result in a resource leak?

> -					ret = 0;
> -					goto fail_alias;
> +					disabled = true;
> +					continue;
>  				}
>  
>  				ret = mfd_match_of_node_to_dev(pdev, np, cell);
> @@ -197,10 +198,17 @@ static int mfd_add_device(struct device *parent, int id,
>  				if (ret)
>  					goto fail_alias;
>  
> -				break;
> +				goto match;
>  			}
>  		}
>  
> +		if (disabled) {
> +			/* Ignore 'disabled' devices error free */
> +			ret = 0;
> +			goto fail_alias;
> +		}
> +
> +match:
>  		if (!pdev->dev.of_node)
>  			pr_warn("%s: Failed to locate of_node [id: %d]\n",
>  				cell->name, platform_id);
> -- 
> 2.41.0
> 

-- 
Lee Jones [李琼斯]

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Re: [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting

[Herve Codina]

Hi Lee,

On Thu, 27 Jul 2023 10:22:09 +0100
Lee Jones <lee@kernel.org> wrote:

> On Wed, 26 Jul 2023, Herve Codina wrote:
> 
> > The loop searching for a matching device based on its compatible
> > string is aborted when a matching disabled device is found.
> > This abort avoid to add devices as soon as one disabled device
> > is found.
> > 
> > Continue searching for an other device instead of aborting on the
> > first disabled one fixes the issue.
> > 
> > Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored without error")
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  drivers/mfd/mfd-core.c | 18 +++++++++++++-----
> >  1 file changed, 13 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
> > index 0ed7c0d7784e..bcc26e64639a 100644
> > --- a/drivers/mfd/mfd-core.c
> > +++ b/drivers/mfd/mfd-core.c
> > @@ -146,6 +146,7 @@ static int mfd_add_device(struct device *parent, int id,
> >  	struct platform_device *pdev;
> >  	struct device_node *np = NULL;
> >  	struct mfd_of_node_entry *of_entry, *tmp;
> > +	bool disabled;
> >  	int ret = -ENOMEM;
> >  	int platform_id;
> >  	int r;
> > @@ -181,13 +182,13 @@ static int mfd_add_device(struct device *parent, int id,
> >  		goto fail_res;
> >  
> >  	if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
> > +		disabled = false;  
> 
> This does not appear to reside in a loop.
> 
> Why not set it to false on declaration?

Indeed, I will change in the next iteration and set the value to false at
the declaration.

> 
> >  		for_each_child_of_node(parent->of_node, np) {
> >  			if (of_device_is_compatible(np, cell->of_compatible)) {
> > -				/* Ignore 'disabled' devices error free */
> > +				/* Skip 'disabled' devices */
> >  				if (!of_device_is_available(np)) {
> > -					of_node_put(np);  
> 
> Doesn't this result in a resource leak?

No because we change from 'goto fail_alias' to 'continue' and so we don't
exit from the for_each_child_of_node().
The for_each_child_of_node() calls of_get_next_child() and, in turn, calls
of_node_put().

Regards,
Hervé

> 
> > -					ret = 0;
> > -					goto fail_alias;
> > +					disabled = true;
> > +					continue;
> >  				}
> >  
> >  				ret = mfd_match_of_node_to_dev(pdev, np, cell);
> > @@ -197,10 +198,17 @@ static int mfd_add_device(struct device *parent, int id,
> >  				if (ret)
> >  					goto fail_alias;
> >  
> > -				break;
> > +				goto match;
> >  			}
> >  		}
> >  
> > +		if (disabled) {
> > +			/* Ignore 'disabled' devices error free */
> > +			ret = 0;
> > +			goto fail_alias;
> > +		}
> > +
> > +match:
> >  		if (!pdev->dev.of_node)
> >  			pr_warn("%s: Failed to locate of_node [id: %d]\n",
> >  				cell->name, platform_id);
> > -- 
> > 2.41.0
> >   
> 


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Re: [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The loop searching for a matching device based on its compatible
> string is aborted when a matching disabled device is found.
> This abort avoid to add devices as soon as one disabled device
> is found.

s/avoid/prevents/

> 
> Continue searching for an other device instead of aborting on the
> first disabled one fixes the issue.
> 
> Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored without error")
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/mfd/mfd-core.c | 18 +++++++++++++-----
>   1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
> index 0ed7c0d7784e..bcc26e64639a 100644
> --- a/drivers/mfd/mfd-core.c
> +++ b/drivers/mfd/mfd-core.c
> @@ -146,6 +146,7 @@ static int mfd_add_device(struct device *parent, int id,
>   	struct platform_device *pdev;
>   	struct device_node *np = NULL;
>   	struct mfd_of_node_entry *of_entry, *tmp;
> +	bool disabled;
>   	int ret = -ENOMEM;
>   	int platform_id;
>   	int r;
> @@ -181,13 +182,13 @@ static int mfd_add_device(struct device *parent, int id,
>   		goto fail_res;
>   
>   	if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
> +		disabled = false;
>   		for_each_child_of_node(parent->of_node, np) {
>   			if (of_device_is_compatible(np, cell->of_compatible)) {
> -				/* Ignore 'disabled' devices error free */
> +				/* Skip 'disabled' devices */
>   				if (!of_device_is_available(np)) {
> -					of_node_put(np);
> -					ret = 0;
> -					goto fail_alias;
> +					disabled = true;
> +					continue;
>   				}
>   
>   				ret = mfd_match_of_node_to_dev(pdev, np, cell);
> @@ -197,10 +198,17 @@ static int mfd_add_device(struct device *parent, int id,
>   				if (ret)
>   					goto fail_alias;
>   
> -				break;
> +				goto match;
>   			}
>   		}
>   
> +		if (disabled) {
> +			/* Ignore 'disabled' devices error free */
> +			ret = 0;
> +			goto fail_alias;
> +		}
> +
> +match:
>   		if (!pdev->dev.of_node)
>   			pr_warn("%s: Failed to locate of_node [id: %d]\n",
>   				cell->name, platform_id);
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Re: [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting

[Herve Codina]

On Tue, 8 Aug 2023 08:13:27 +0000
Christophe Leroy <christophe.leroy@csgroup.eu> wrote:

> Le 26/07/2023 à 17:02, Herve Codina a écrit :
> > The loop searching for a matching device based on its compatible
> > string is aborted when a matching disabled device is found.
> > This abort avoid to add devices as soon as one disabled device
> > is found.  
> 
> s/avoid/prevents/

Yes, will be changed.

> 
> > 
> > Continue searching for an other device instead of aborting on the
> > first disabled one fixes the issue.
> > 
> > Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored without error")
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>  
> 
> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> 


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Re: [PATCH v2 25/28] MAINTAINERS: Add the Lantiq PEF2256 driver entry

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> After contributing the driver, add myself as the maintainer for the
> Lantiq PEF2256 driver.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   MAINTAINERS | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 14041d90f9c8..07a7d9fca3c4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11776,6 +11776,15 @@ S:	Maintained
>   F:	arch/mips/lantiq
>   F:	drivers/soc/lantiq
>   
> +LANTIQ PEF2256 DRIVER
> +M:	Herve Codina <herve.codina@bootlin.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> +F:	drivers/net/wan/framer/pef2256/
> +F:	drivers/pinctrl/pinctrl-pef2256-regs.h
> +F:	drivers/pinctrl/pinctrl-pef2256.c
> +F:	include/linux/framer/pef2256.h
> +
>   LASI 53c700 driver for PARISC
>   M:	"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
>   L:	linux-scsi@vger.kernel.org
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Re: [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec

[Andrew Lunn]

On Wed, Jul 26, 2023 at 05:02:22PM +0200, Herve Codina wrote:
> The framer codec interracts with a framer.
> It allows to use some of the framer timeslots as audio channels to
> transport audio data over the framer E1/T1/J1 lines.
> It also reports line carrier detection events through the ALSA jack
> detection feature.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  sound/soc/codecs/Kconfig        |  15 ++
>  sound/soc/codecs/Makefile       |   2 +
>  sound/soc/codecs/framer-codec.c | 423 ++++++++++++++++++++++++++++++++
>  3 files changed, 440 insertions(+)
>  create mode 100644 sound/soc/codecs/framer-codec.c
> 
> diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
> index f99203ef9b03..a86cdac39b72 100644
> --- a/sound/soc/codecs/Kconfig
> +++ b/sound/soc/codecs/Kconfig
> @@ -110,6 +110,7 @@ config SND_SOC_ALL_CODECS
>  	imply SND_SOC_ES8328_I2C
>  	imply SND_SOC_ES7134
>  	imply SND_SOC_ES7241
> +	imply SND_SOC_FRAMER
>  	imply SND_SOC_GTM601
>  	imply SND_SOC_HDAC_HDMI
>  	imply SND_SOC_HDAC_HDA
> @@ -1043,6 +1044,20 @@ config SND_SOC_ES8328_SPI
>  	depends on SPI_MASTER
>  	select SND_SOC_ES8328
>  
> +config SND_SOC_FRAMER
> +	tristate "Framer codec"
> +	depends on GENERIC_FRAMER
> +	help
> +	  Enable support for the framer codec.
> +	  The framer codec uses the generic framer infrastructure to transport
> +	  some audio data over an analog E1/T1/J1 line.
> +	  This codec allows to use some of the time slots available on the TDM
> +	  bus on which the framer is connected to transport the audio data.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called snd-soc-framer.
> +
> +
>  config SND_SOC_GTM601
>  	tristate 'GTM601 UMTS modem audio codec'
>  
> diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
> index 32dcc6de58bd..54667274a0f6 100644
> --- a/sound/soc/codecs/Makefile
> +++ b/sound/soc/codecs/Makefile
> @@ -116,6 +116,7 @@ snd-soc-es8326-objs := es8326.o
>  snd-soc-es8328-objs := es8328.o
>  snd-soc-es8328-i2c-objs := es8328-i2c.o
>  snd-soc-es8328-spi-objs := es8328-spi.o
> +snd-soc-framer-objs := framer-codec.o
>  snd-soc-gtm601-objs := gtm601.o
>  snd-soc-hdac-hdmi-objs := hdac_hdmi.o
>  snd-soc-hdac-hda-objs := hdac_hda.o
> @@ -499,6 +500,7 @@ obj-$(CONFIG_SND_SOC_ES8326)    += snd-soc-es8326.o
>  obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o
>  obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
>  obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
> +obj-$(CONFIG_SND_SOC_FRAMER)	+= snd-soc-framer.o
>  obj-$(CONFIG_SND_SOC_GTM601)    += snd-soc-gtm601.o
>  obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
>  obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-soc-hdac-hda.o
> diff --git a/sound/soc/codecs/framer-codec.c b/sound/soc/codecs/framer-codec.c
> new file mode 100644
> index 000000000000..52b4546a61ee
> --- /dev/null
> +++ b/sound/soc/codecs/framer-codec.c
> @@ -0,0 +1,423 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Framer ALSA SoC driver
> +//
> +// Copyright 2023 CS GROUP France
> +//
> +// Author: Herve Codina <herve.codina@bootlin.com>
> +
> +#include <linux/clk.h>
> +#include <linux/framer/framer.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <sound/jack.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include <sound/tlv.h>
> +
> +#define FRAMER_NB_CHANNEL	32
> +#define FRAMER_JACK_MASK (SND_JACK_LINEIN | SND_JACK_LINEOUT)
> +
> +struct framer_codec {
> +	struct framer *framer;
> +	struct device *dev;
> +	struct snd_soc_jack jack;
> +	struct notifier_block nb;
> +	struct work_struct carrier_work;
> +	int max_chan_playback;
> +	int max_chan_capture;
> +};
> +
> +static int framer_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
> +				   unsigned int rx_mask, int slots, int width)
> +{
> +	struct framer_codec *framer = snd_soc_component_get_drvdata(dai->component);
> +
> +	switch (width) {
> +	case 0:
> +		/* Not set -> default 8 */
> +	case 8:
> +		break;
> +	default:
> +		dev_err(dai->dev, "tdm slot width %d not supported\n", width);
> +		return -EINVAL;
> +	}
> +
> +	framer->max_chan_playback = hweight32(tx_mask);
> +	if (framer->max_chan_playback > FRAMER_NB_CHANNEL) {
> +		dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n",

"many", not "much".

Also, "supported".

      Andrew

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Re: [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec

[Herve Codina]

On Tue, 1 Aug 2023 12:30:26 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> On Wed, Jul 26, 2023 at 05:02:22PM +0200, Herve Codina wrote:
> > The framer codec interracts with a framer.
> > It allows to use some of the framer timeslots as audio channels to
> > transport audio data over the framer E1/T1/J1 lines.
> > It also reports line carrier detection events through the ALSA jack
> > detection feature.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  sound/soc/codecs/Kconfig        |  15 ++
> >  sound/soc/codecs/Makefile       |   2 +
> >  sound/soc/codecs/framer-codec.c | 423 ++++++++++++++++++++++++++++++++
> >  3 files changed, 440 insertions(+)
> >  create mode 100644 sound/soc/codecs/framer-codec.c
> > 
> > diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
> > index f99203ef9b03..a86cdac39b72 100644
> > --- a/sound/soc/codecs/Kconfig
> > +++ b/sound/soc/codecs/Kconfig
> > @@ -110,6 +110,7 @@ config SND_SOC_ALL_CODECS
> >  	imply SND_SOC_ES8328_I2C
> >  	imply SND_SOC_ES7134
> >  	imply SND_SOC_ES7241
> > +	imply SND_SOC_FRAMER
> >  	imply SND_SOC_GTM601
> >  	imply SND_SOC_HDAC_HDMI
> >  	imply SND_SOC_HDAC_HDA
> > @@ -1043,6 +1044,20 @@ config SND_SOC_ES8328_SPI
> >  	depends on SPI_MASTER
> >  	select SND_SOC_ES8328
> >  
> > +config SND_SOC_FRAMER
> > +	tristate "Framer codec"
> > +	depends on GENERIC_FRAMER
> > +	help
> > +	  Enable support for the framer codec.
> > +	  The framer codec uses the generic framer infrastructure to transport
> > +	  some audio data over an analog E1/T1/J1 line.
> > +	  This codec allows to use some of the time slots available on the TDM
> > +	  bus on which the framer is connected to transport the audio data.
> > +
> > +	  To compile this driver as a module, choose M here: the module
> > +	  will be called snd-soc-framer.
> > +
> > +
> >  config SND_SOC_GTM601
> >  	tristate 'GTM601 UMTS modem audio codec'
> >  
> > diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
> > index 32dcc6de58bd..54667274a0f6 100644
> > --- a/sound/soc/codecs/Makefile
> > +++ b/sound/soc/codecs/Makefile
> > @@ -116,6 +116,7 @@ snd-soc-es8326-objs := es8326.o
> >  snd-soc-es8328-objs := es8328.o
> >  snd-soc-es8328-i2c-objs := es8328-i2c.o
> >  snd-soc-es8328-spi-objs := es8328-spi.o
> > +snd-soc-framer-objs := framer-codec.o
> >  snd-soc-gtm601-objs := gtm601.o
> >  snd-soc-hdac-hdmi-objs := hdac_hdmi.o
> >  snd-soc-hdac-hda-objs := hdac_hda.o
> > @@ -499,6 +500,7 @@ obj-$(CONFIG_SND_SOC_ES8326)    += snd-soc-es8326.o
> >  obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o
> >  obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
> >  obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
> > +obj-$(CONFIG_SND_SOC_FRAMER)	+= snd-soc-framer.o
> >  obj-$(CONFIG_SND_SOC_GTM601)    += snd-soc-gtm601.o
> >  obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
> >  obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-soc-hdac-hda.o
> > diff --git a/sound/soc/codecs/framer-codec.c b/sound/soc/codecs/framer-codec.c
> > new file mode 100644
> > index 000000000000..52b4546a61ee
> > --- /dev/null
> > +++ b/sound/soc/codecs/framer-codec.c
> > @@ -0,0 +1,423 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Framer ALSA SoC driver
> > +//
> > +// Copyright 2023 CS GROUP France
> > +//
> > +// Author: Herve Codina <herve.codina@bootlin.com>
> > +
> > +#include <linux/clk.h>
> > +#include <linux/framer/framer.h>
> > +#include <linux/module.h>
> > +#include <linux/notifier.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <sound/jack.h>
> > +#include <sound/pcm_params.h>
> > +#include <sound/soc.h>
> > +#include <sound/tlv.h>
> > +
> > +#define FRAMER_NB_CHANNEL	32
> > +#define FRAMER_JACK_MASK (SND_JACK_LINEIN | SND_JACK_LINEOUT)
> > +
> > +struct framer_codec {
> > +	struct framer *framer;
> > +	struct device *dev;
> > +	struct snd_soc_jack jack;
> > +	struct notifier_block nb;
> > +	struct work_struct carrier_work;
> > +	int max_chan_playback;
> > +	int max_chan_capture;
> > +};
> > +
> > +static int framer_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
> > +				   unsigned int rx_mask, int slots, int width)
> > +{
> > +	struct framer_codec *framer = snd_soc_component_get_drvdata(dai->component);
> > +
> > +	switch (width) {
> > +	case 0:
> > +		/* Not set -> default 8 */
> > +	case 8:
> > +		break;
> > +	default:
> > +		dev_err(dai->dev, "tdm slot width %d not supported\n", width);
> > +		return -EINVAL;
> > +	}
> > +
> > +	framer->max_chan_playback = hweight32(tx_mask);
> > +	if (framer->max_chan_playback > FRAMER_NB_CHANNEL) {
> > +		dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n",  
> 
> "many", not "much".
> 
> Also, "supported".

Yes, will be fixed.

Regards,
Hervé

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Re: [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> The framer codec interracts with a framer.
> It allows to use some of the framer timeslots as audio channels to
> transport audio data over the framer E1/T1/J1 lines.
> It also reports line carrier detection events through the ALSA jack
> detection feature.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

See below

> +static int framer_dai_hw_rule_channels_by_format(struct snd_soc_dai *dai,
> +						 struct snd_pcm_hw_params *params,
> +						 unsigned int nb_ts)
> +{
> +	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
> +	snd_pcm_format_t format = params_format(params);
> +	struct snd_interval ch = {0};
> +
> +	switch (snd_pcm_format_physical_width(format)) {
> +	case 8:
> +		ch.max = nb_ts;
> +		break;
> +	case 16:
> +		ch.max = nb_ts / 2;
> +		break;
> +	case 32:
> +		ch.max = nb_ts / 4;
> +		break;
> +	case 64:
> +		ch.max = nb_ts / 8;
> +		break;
> +	default:
> +		dev_err(dai->dev, "format physical width %u not supported\n",
> +			snd_pcm_format_physical_width(format));
> +		return -EINVAL;
> +	}

What about

	width = snd_pcm_format_physical_width(format);

	if (width == 8 || width == 16 || width == 32 || width == 64) {
		ch.max = nb_ts * 8 / width;
	} else {
		dev_err(dai->dev, "format physical width %u not supported\n", width);
		return -EINVAL;
	}

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Re: [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec

[Herve Codina]

On Tue, 8 Aug 2023 08:26:16 +0000
Christophe Leroy <christophe.leroy@csgroup.eu> wrote:

> Le 26/07/2023 à 17:02, Herve Codina a écrit :
> > The framer codec interracts with a framer.
> > It allows to use some of the framer timeslots as audio channels to
> > transport audio data over the framer E1/T1/J1 lines.
> > It also reports line carrier detection events through the ALSA jack
> > detection feature.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>  
> 
> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> 
> See below
> 
> > +static int framer_dai_hw_rule_channels_by_format(struct snd_soc_dai *dai,
> > +						 struct snd_pcm_hw_params *params,
> > +						 unsigned int nb_ts)
> > +{
> > +	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
> > +	snd_pcm_format_t format = params_format(params);
> > +	struct snd_interval ch = {0};
> > +
> > +	switch (snd_pcm_format_physical_width(format)) {
> > +	case 8:
> > +		ch.max = nb_ts;
> > +		break;
> > +	case 16:
> > +		ch.max = nb_ts / 2;
> > +		break;
> > +	case 32:
> > +		ch.max = nb_ts / 4;
> > +		break;
> > +	case 64:
> > +		ch.max = nb_ts / 8;
> > +		break;
> > +	default:
> > +		dev_err(dai->dev, "format physical width %u not supported\n",
> > +			snd_pcm_format_physical_width(format));
> > +		return -EINVAL;
> > +	}  
> 
> What about
> 
> 	width = snd_pcm_format_physical_width(format);
> 
> 	if (width == 8 || width == 16 || width == 32 || width == 64) {
> 		ch.max = nb_ts * 8 / width;
> 	} else {
> 		dev_err(dai->dev, "format physical width %u not supported\n", width);
> 		return -EINVAL;
> 	}
> 

Yes, indeed.
Will be changed in the next iteration.

Regards,
Hervé

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Re: [PATCH v2 28/28] net: wan: fsl_qmc_hdlc: Add framer support

[Christophe Leroy]

Le 26/07/2023 à 17:02, Herve Codina a écrit :
> Add framer support in the fsl_qmc_hdlc driver in order to be able to
> signal carrier changes to the network stack based on the framer status
> Also use this framer to provide information related to the E1/T1 line
> interface on IF_GET_IFACE and configure the line interface according to
> IF_IFACE_{E1,T1} information.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
>   drivers/net/wan/fsl_qmc_hdlc.c | 239 ++++++++++++++++++++++++++++++++-
>   1 file changed, 235 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
> index c449edf0a35e..a873071fa5ca 100644
> --- a/drivers/net/wan/fsl_qmc_hdlc.c
> +++ b/drivers/net/wan/fsl_qmc_hdlc.c
> @@ -8,6 +8,7 @@
>    */
>   
>   #include <linux/dma-mapping.h>
> +#include <linux/framer/framer.h>
>   #include <linux/hdlc.h>
>   #include <linux/module.h>
>   #include <linux/of.h>
> @@ -27,6 +28,9 @@ struct qmc_hdlc {
>   	struct device *dev;
>   	struct qmc_chan *qmc_chan;
>   	struct net_device *netdev;
> +	struct framer *framer;
> +	spinlock_t carrier_lock; /* Protect carrier detection */
> +	struct notifier_block nb;
>   	bool is_crc32;
>   	spinlock_t tx_lock; /* Protect tx descriptors */
>   	struct qmc_hdlc_desc tx_descs[8];
> @@ -40,6 +44,195 @@ static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
>   	return (struct qmc_hdlc *)dev_to_hdlc(netdev)->priv;
>   }
>   
> +static int qmc_hdlc_framer_set_carrier(struct qmc_hdlc *qmc_hdlc)
> +{
> +	struct framer_status framer_status;
> +	unsigned long flags;
> +	int ret;
> +
> +	if (!qmc_hdlc->framer)
> +		return 0;
> +
> +	spin_lock_irqsave(&qmc_hdlc->carrier_lock, flags);
> +
> +	ret = framer_get_status(qmc_hdlc->framer, &framer_status);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
> +		goto end;
> +	}
> +	if (framer_status.link_is_on)
> +		netif_carrier_on(qmc_hdlc->netdev);
> +	else
> +		netif_carrier_off(qmc_hdlc->netdev);
> +
> +end:
> +	spin_unlock_irqrestore(&qmc_hdlc->carrier_lock, flags);
> +	return ret;
> +}
> +
> +static int qmc_hdlc_framer_notifier(struct notifier_block *nb, unsigned long action,
> +				    void *data)
> +{
> +	struct qmc_hdlc *qmc_hdlc = container_of(nb, struct qmc_hdlc, nb);
> +	int ret;
> +
> +	if (action != FRAMER_EVENT_STATUS)
> +		return NOTIFY_DONE;
> +
> +	ret = qmc_hdlc_framer_set_carrier(qmc_hdlc);
> +	return ret ? NOTIFY_DONE : NOTIFY_OK;
> +}
> +
> +static int qmc_hdlc_framer_start(struct qmc_hdlc *qmc_hdlc)
> +{
> +	struct framer_status framer_status;
> +	int ret;
> +
> +	if (!qmc_hdlc->framer)
> +		return 0;
> +
> +	ret = framer_power_on(qmc_hdlc->framer);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "framer power-on failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	/* Be sure that get_status is supported */
> +	ret = framer_get_status(qmc_hdlc->framer, &framer_status);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
> +		goto framer_power_off;
> +	}
> +
> +	qmc_hdlc->nb.notifier_call = qmc_hdlc_framer_notifier;
> +	ret = framer_notifier_register(qmc_hdlc->framer, &qmc_hdlc->nb);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "framer notifier register failed (%d)\n", ret);
> +		goto framer_power_off;
> +	}
> +
> +	return 0;
> +
> +framer_power_off:
> +	framer_power_off(qmc_hdlc->framer);
> +	return ret;
> +}
> +
> +static void qmc_hdlc_framer_stop(struct qmc_hdlc *qmc_hdlc)
> +{
> +	if (!qmc_hdlc->framer)
> +		return;
> +
> +	framer_notifier_unregister(qmc_hdlc->framer, &qmc_hdlc->nb);
> +	framer_power_off(qmc_hdlc->framer);
> +}
> +
> +static int qmc_hdlc_framer_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface,
> +				     const te1_settings *te1)
> +{
> +	struct framer_config config;
> +	int ret;
> +
> +	if (!qmc_hdlc->framer)
> +		return 0;
> +
> +	ret = framer_get_config(qmc_hdlc->framer, &config);
> +	if (ret)
> +		return ret;
> +
> +	switch (if_iface) {
> +	case IF_IFACE_E1:
> +		config.iface = FRAMER_IFACE_E1;
> +		break;
> +	case IF_IFACE_T1:
> +		config.iface = FRAMER_IFACE_T1;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	switch (te1->clock_type) {
> +	case CLOCK_DEFAULT:
> +		/* Keep current value */
> +		break;
> +	case CLOCK_EXT:
> +		config.clock_type = FRAMER_CLOCK_EXT;
> +		break;
> +	case CLOCK_INT:
> +		config.clock_type = FRAMER_CLOCK_INT;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +	config.line_clock_rate = te1->clock_rate;
> +
> +	return framer_set_config(qmc_hdlc->framer, &config);
> +}
> +
> +static int qmc_hdlc_framer_get_iface(struct qmc_hdlc *qmc_hdlc, int *if_iface, te1_settings *te1)
> +{
> +	struct framer_config config;
> +	int ret;
> +
> +	if (!qmc_hdlc->framer) {
> +		*if_iface = IF_IFACE_E1;
> +		return 0;
> +	}
> +
> +	ret = framer_get_config(qmc_hdlc->framer, &config);
> +	if (ret)
> +		return ret;
> +
> +	switch (config.iface) {
> +	case FRAMER_IFACE_E1:
> +		*if_iface = IF_IFACE_E1;
> +		break;
> +	case FRAMER_IFACE_T1:
> +		*if_iface = IF_IFACE_T1;
> +		break;
> +	}
> +
> +	if (!te1)
> +		return 0; /* Only iface type requested */
> +
> +	switch (config.clock_type) {
> +	case FRAMER_CLOCK_EXT:
> +		te1->clock_type = CLOCK_EXT;
> +		break;
> +	case FRAMER_CLOCK_INT:
> +		te1->clock_type = CLOCK_INT;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +	te1->clock_rate = config.line_clock_rate;
> +	return 0;
> +}
> +
> +static int qmc_hdlc_framer_init(struct qmc_hdlc *qmc_hdlc)
> +{
> +	int ret;
> +
> +	if (!qmc_hdlc->framer)
> +		return 0;
> +
> +	ret = framer_init(qmc_hdlc->framer);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "framer init failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void qmc_hdlc_framer_exit(struct qmc_hdlc *qmc_hdlc)
> +{
> +	if (!qmc_hdlc->framer)
> +		return;
> +
> +	framer_exit(qmc_hdlc->framer);
> +}
> +
>   static int qmc_hdlc_recv_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc *desc, size_t size);
>   
>   #define QMC_HDLC_RX_ERROR_FLAGS (QMC_RX_FLAG_HDLC_OVF | \
> @@ -313,6 +506,12 @@ static int qmc_hdlc_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface, const te1
>   
>   	qmc_hdlc->slot_map = te1->slot_map;
>   
> +	ret = qmc_hdlc_framer_set_iface(qmc_hdlc, if_iface, te1);
> +	if (ret) {
> +		dev_err(qmc_hdlc->dev, "framer set iface failed %d\n", ret);
> +		return ret;
> +	}
> +
>   	return 0;
>   }
>   
> @@ -320,11 +519,16 @@ static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
>   {
>   	struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
>   	te1_settings te1;
> +	int ret;
>   
>   	switch (ifs->type) {
>   	case IF_GET_IFACE:
> -		ifs->type = IF_IFACE_E1;
>   		if (ifs->size < sizeof(te1)) {
> +			/* Retrieve type only */
> +			ret = qmc_hdlc_framer_get_iface(qmc_hdlc, &ifs->type, NULL);
> +			if (ret)
> +				return ret;
> +
>   			if (!ifs->size)
>   				return 0; /* only type requested */
>   
> @@ -334,6 +538,11 @@ static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
>   
>   		memset(&te1, 0, sizeof(te1));
>   
> +		/* Retrieve info from framer */
> +		ret = qmc_hdlc_framer_get_iface(qmc_hdlc, &ifs->type, &te1);
> +		if (ret)
> +			return ret;
> +
>   		/* Update slot_map */
>   		te1.slot_map = qmc_hdlc->slot_map;
>   
> @@ -367,10 +576,17 @@ static int qmc_hdlc_open(struct net_device *netdev)
>   	int ret;
>   	int i;
>   
> -	ret = hdlc_open(netdev);
> +	ret = qmc_hdlc_framer_start(qmc_hdlc);
>   	if (ret)
>   		return ret;
>   
> +	ret = hdlc_open(netdev);
> +	if (ret)
> +		goto framer_stop;
> +
> +	/* Update carrier */
> +	qmc_hdlc_framer_set_carrier(qmc_hdlc);
> +
>   	chan_param.mode = QMC_HDLC;
>   	/* HDLC_MAX_MRU + 4 for the CRC
>   	 * HDLC_MAX_MRU + 4 + 8 for the CRC and some extraspace needed by the QMC
> @@ -420,6 +636,8 @@ static int qmc_hdlc_open(struct net_device *netdev)
>   	}
>   hdlc_close:
>   	hdlc_close(netdev);
> +framer_stop:
> +	qmc_hdlc_framer_stop(qmc_hdlc);
>   	return ret;
>   }
>   
> @@ -455,6 +673,7 @@ static int qmc_hdlc_close(struct net_device *netdev)
>   	}
>   
>   	hdlc_close(netdev);
> +	qmc_hdlc_framer_stop(qmc_hdlc);
>   	return 0;
>   }
>   
> @@ -503,6 +722,7 @@ static int qmc_hdlc_probe(struct platform_device *pdev)
>   
>   	qmc_hdlc->dev = &pdev->dev;
>   	spin_lock_init(&qmc_hdlc->tx_lock);
> +	spin_lock_init(&qmc_hdlc->carrier_lock);
>   
>   	qmc_hdlc->qmc_chan = devm_qmc_chan_get_byphandle(qmc_hdlc->dev, np, "fsl,qmc-chan");
>   	if (IS_ERR(qmc_hdlc->qmc_chan)) {
> @@ -531,10 +751,19 @@ static int qmc_hdlc_probe(struct platform_device *pdev)
>   	if (ret)
>   		return ret;
>   
> +	qmc_hdlc->framer = devm_framer_optional_get(qmc_hdlc->dev, "framer");
> +	if (IS_ERR(qmc_hdlc->framer))
> +		return PTR_ERR(qmc_hdlc->framer);
> +
> +	ret = qmc_hdlc_framer_init(qmc_hdlc);
> +	if (ret)
> +		return ret;
> +
>   	qmc_hdlc->netdev = alloc_hdlcdev(qmc_hdlc);
>   	if (!qmc_hdlc->netdev) {
>   		dev_err(qmc_hdlc->dev, "failed to alloc hdlc dev\n");
> -		return -ENOMEM;
> +		ret = -ENOMEM;
> +		goto framer_exit;
>   	}
>   
>   	hdlc = dev_to_hdlc(qmc_hdlc->netdev);
> @@ -550,11 +779,12 @@ static int qmc_hdlc_probe(struct platform_device *pdev)
>   	}
>   
>   	platform_set_drvdata(pdev, qmc_hdlc);
> -
>   	return 0;
>   
>   free_netdev:
>   	free_netdev(qmc_hdlc->netdev);
> +framer_exit:
> +	qmc_hdlc_framer_exit(qmc_hdlc);
>   	return ret;
>   }
>   
> @@ -564,6 +794,7 @@ static int qmc_hdlc_remove(struct platform_device *pdev)
>   
>   	unregister_hdlc_device(qmc_hdlc->netdev);
>   	free_netdev(qmc_hdlc->netdev);
> +	qmc_hdlc_framer_exit(qmc_hdlc);
>   
>   	return 0;
>   }
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