From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 791CFC77B7F for ; Fri, 18 Aug 2023 16:11:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eFLfpEOkxJFTY18IvvSwSUFwbKqooQzXJqgrVGd240c=; b=moPRp0LdqympbX fk3q6kAts/A9HCOIXU8lFjafzGMNkjAUFTSjABt2JZeTZEf5KZ6ofYmHp0QwVgeHPdhuRJHai3fKQ fplOzuPMR7dwluJguiT2u5QBr2gUzEswWsFXCWj6LQXs1wUEvyT3laeTWAuEQTfLToLHllKhnJ9Yq YMMVpLpTiWfeOuJWvxWL81aPzMSWY5c/LxmNTlYyo3/yjncgzlJbhsY7ypADOr1hepRf4HTPs71m+ 8AyT/5adFN1ifhmOqmygE4Ct8CdOpjbvyItd3wLjrqUocSfzyXZ5PSt+I3hhGMhw8OLJZ43e7BNh8 +cvogS/KQXBCWTekht6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qX24O-009eC5-1O; Fri, 18 Aug 2023 16:11:28 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qX24L-009eBl-0k for linux-arm-kernel@lists.infradead.org; Fri, 18 Aug 2023 16:11:26 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B470260B3A; Fri, 18 Aug 2023 16:11:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 759E9C433C7; Fri, 18 Aug 2023 16:11:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692375084; bh=+gzO0gKiOTRvCJKQsYSXROLf2cSwuATfh8XfDlyDbx4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ePlCY5fFLfTm9fu9uOgrC8vID6pmWPF3IhzlNcRfiyIwCNyPfW1OJtn9UtAY6XmmJ 30VZEPFtEWomODVYC7C/7CylpIyZ0S6HMK31+bppdDlimHRcQbIEz1OB77jqDgXFKw fJY+Tlos4YGqlH21Q3LXS39C+f5dOdk1a2DubODM697WU3Kc/k+lbJWhB1o5nvpgNN rqsmt5NKhF3ZuiqmM+KCiokVMpqn50n5JURg2VTNZuwk1gb51khD19irICWbaogpGN 9Px3+jtCisHbYjCA4zDLGoMIAxwYsdu6kyf7l1N5r2z3DZ0fgFImHKoW3IuEDgTO6O pUCuDTKgC3yDw== Date: Fri, 18 Aug 2023 17:11:19 +0100 From: Will Deacon To: Nicolin Chen Cc: robin.murphy@arm.com, jgg@nvidia.com, joro@8bytes.org, jean-philippe@linaro.org, apopple@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Add a user-configurable tlb_invalidate_threshold Message-ID: <20230818161119.GA16216@willie-the-truck> References: <20230816204350.29150-1-nicolinc@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230818_091125_328861_DF0BA880 X-CRM114-Status: GOOD ( 21.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 17, 2023 at 11:36:18AM -0700, Nicolin Chen wrote: > On Wed, Aug 16, 2023 at 01:43:50PM -0700, Nicolin Chen wrote: > > > When receiving an __arm_smmu_tlb_inv_range() call with a large size, there > > could be a long latency at this function call: one part is coming from a > > large software overhead in the routine of building commands, and the other > > part is coming from CMDQ hardware consuming the large number of commands. > > This latency could be significantly large on an SMMU that does not support > > range invalidation commands, i.e. no ARM_SMMU_FEAT_RANGE_INV. > > > > One way to optimize this is to replace a large number of VA invalidation > > commands with one single per-asid invalidation command, when the requested > > size reaches a threshold. This threshold can be configurable depending on > > the SMMU implementaion. > > I'm rethinking about this size-based threshold, since what really > affects the latency is the number of the invalidation commands in > the request. So having an npages-based threshold might be optimal, > though the idea and implementation would be similar. On the CPU side, we just have: #define MAX_TLBI_OPS PTRS_PER_PTE in asm/tlbflush.h Can we start off with something similar for the SMMU? I'm not massively keen on exposing this as a knob to userspace, because I don't think most people will have a clue about how to tune it. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel