From: Jing Zhang <jingzhangos@google.com>
To: KVM <kvm@vger.kernel.org>, KVMARM <kvmarm@lists.linux.dev>,
ARMLinux <linux-arm-kernel@lists.infradead.org>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>
Cc: Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Fuad Tabba <tabba@google.com>,
Reiji Watanabe <reijiw@google.com>,
Raghavendra Rao Ananta <rananta@google.com>,
Suraj Jitindar Singh <surajjs@amazon.com>,
Cornelia Huck <cohuck@redhat.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>
Subject: [PATCH v9 08/11] KVM: arm64: Refactor helper Macros for idreg desc
Date: Mon, 21 Aug 2023 14:22:40 -0700 [thread overview]
Message-ID: <20230821212243.491660-9-jingzhangos@google.com> (raw)
In-Reply-To: <20230821212243.491660-1-jingzhangos@google.com>
Add some helpers to ease the declaration for idreg desc.
These Macros will be heavily used for future commits enabling writable
for idregs.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/sys_regs.c | 82 +++++++++++++++++----------------------
1 file changed, 36 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index bf716f646872..44d164d47756 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1844,27 +1844,37 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
* from userspace.
*/
-/* sys_reg_desc initialiser for known cpufeature ID registers */
-#define ID_SANITISED(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = id_visibility, \
- .reset = kvm_read_sanitised_id_reg, \
- .val = 0, \
+#define ID_DESC(name, _set_user, _visibility, _reset, mask) { \
+ SYS_DESC(SYS_##name), \
+ .access = access_id_reg, \
+ .get_user = get_id_reg, \
+ .set_user = _set_user, \
+ .visibility = _visibility, \
+ .reset = _reset, \
+ .val = mask, \
}
/* sys_reg_desc initialiser for known cpufeature ID registers */
-#define AA32_ID_SANITISED(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = aa32_id_visibility, \
- .reset = kvm_read_sanitised_id_reg, \
- .val = 0, \
-}
+#define _ID_SANITISED(name, _set_user, _reset) \
+ ID_DESC(name, _set_user, id_visibility, _reset, 0)
+#define ID_SANITISED(name) \
+ _ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg)
+
+#define _ID_SANITISED_W(name, _set_user, _reset, mask) \
+ ID_DESC(name, _set_user, id_visibility, _reset, mask)
+#define ID_SANITISED_W(name, mask) \
+ _ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg, mask)
+
+/* sys_reg_desc initialiser for known cpufeature ID registers */
+#define _AA32_ID_SANITISED(name, _set_user, _reset) \
+ ID_DESC(name, _set_user, aa32_id_visibility, _reset, 0)
+#define AA32_ID_SANITISED(name) \
+ _AA32_ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg)
+
+#define _AA32_ID_SANITISED_W(name, _set_user, _reset, mask) \
+ ID_DESC(name, _set_user, aa32_id_visibility, _reset, mask)
+#define AA32_ID_SANITISED_W(name, mask) \
+ _AA32_ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg, mask)
/*
* sys_reg_desc initialiser for architecturally unallocated cpufeature ID
@@ -1886,15 +1896,8 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
* For now, these are exposed just like unallocated ID regs: they appear
* RAZ for the guest.
*/
-#define ID_HIDDEN(name) { \
- SYS_DESC(SYS_##name), \
- .access = access_id_reg, \
- .get_user = get_id_reg, \
- .set_user = set_id_reg, \
- .visibility = raz_visibility, \
- .reset = kvm_read_sanitised_id_reg, \
- .val = 0, \
-}
+#define ID_HIDDEN(name) \
+ ID_DESC(name, set_id_reg, raz_visibility, kvm_read_sanitised_id_reg, 0)
static bool access_sp_el1(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
@@ -2003,13 +2006,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* CRm=1 */
AA32_ID_SANITISED(ID_PFR0_EL1),
AA32_ID_SANITISED(ID_PFR1_EL1),
- { SYS_DESC(SYS_ID_DFR0_EL1),
- .access = access_id_reg,
- .get_user = get_id_reg,
- .set_user = set_id_dfr0_el1,
- .visibility = aa32_id_visibility,
- .reset = read_sanitised_id_dfr0_el1,
- .val = GENMASK(31, 0), },
+ _AA32_ID_SANITISED_W(ID_DFR0_EL1, set_id_dfr0_el1,
+ read_sanitised_id_dfr0_el1, GENMASK(31, 0)),
ID_HIDDEN(ID_AFR0_EL1),
AA32_ID_SANITISED(ID_MMFR0_EL1),
AA32_ID_SANITISED(ID_MMFR1_EL1),
@@ -2038,12 +2036,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* AArch64 ID registers */
/* CRm=4 */
- { SYS_DESC(SYS_ID_AA64PFR0_EL1),
- .access = access_id_reg,
- .get_user = get_id_reg,
- .set_user = set_id_reg,
- .reset = read_sanitised_id_aa64pfr0_el1,
- .val = ~ID_AA64PFR0_EL1_AMU_MASK, },
+ _ID_SANITISED_W(ID_AA64PFR0_EL1, set_id_reg,
+ read_sanitised_id_aa64pfr0_el1, ~ID_AA64PFR0_EL1_AMU_MASK),
ID_SANITISED(ID_AA64PFR1_EL1),
ID_UNALLOCATED(4,2),
ID_UNALLOCATED(4,3),
@@ -2053,12 +2047,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
ID_UNALLOCATED(4,7),
/* CRm=5 */
- { SYS_DESC(SYS_ID_AA64DFR0_EL1),
- .access = access_id_reg,
- .get_user = get_id_reg,
- .set_user = set_id_aa64dfr0_el1,
- .reset = read_sanitised_id_aa64dfr0_el1,
- .val = ~(ID_AA64DFR0_EL1_PMSVer_MASK | ID_AA64DFR0_EL1_RES0_MASK), },
+ _ID_SANITISED_W(ID_AA64DFR0_EL1, set_id_aa64dfr0_el1, read_sanitised_id_aa64dfr0_el1,
+ ~(ID_AA64DFR0_EL1_PMSVer_MASK | ID_AA64DFR0_EL1_RES0_MASK)),
ID_SANITISED(ID_AA64DFR1_EL1),
ID_UNALLOCATED(5,2),
ID_UNALLOCATED(5,3),
--
2.42.0.rc1.204.g551eb34607-goog
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next prev parent reply other threads:[~2023-08-21 21:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-21 21:22 [PATCH v9 00/11] Enable writable for idregs DFR0,PFR0, MMFR{0,1,2,3} Jing Zhang
2023-08-21 21:22 ` [PATCH v9 01/11] KVM: arm64: Allow userspace to get the writable masks for feature ID registers Jing Zhang
2023-08-21 21:22 ` [PATCH v9 02/11] KVM: arm64: Document KVM_ARM_GET_REG_WRITABLE_MASKS Jing Zhang
2023-08-21 21:22 ` [PATCH v9 03/11] KVM: arm64: Use guest ID register values for the sake of emulation Jing Zhang
2023-08-21 21:22 ` [PATCH v9 04/11] KVM: arm64: Reject attempts to set invalid debug arch version Jing Zhang
2023-08-21 21:22 ` [PATCH v9 05/11] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 Jing Zhang
2023-08-22 7:06 ` Marc Zyngier
2023-08-22 18:35 ` Jing Zhang
2023-08-26 10:51 ` Marc Zyngier
2023-08-27 19:31 ` Jing Zhang
2023-09-06 2:13 ` Jing Zhang
2023-09-06 6:03 ` Oliver Upton
2023-08-21 21:22 ` [PATCH v9 06/11] KVM: arm64: Bump up the default KVM sanitised debug version to v8p8 Jing Zhang
2023-08-21 21:22 ` [PATCH v9 07/11] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 Jing Zhang
2023-08-22 7:10 ` Marc Zyngier
2023-08-21 21:22 ` Jing Zhang [this message]
2023-08-21 21:22 ` [PATCH v9 09/11] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 Jing Zhang
2023-08-21 21:22 ` [PATCH v9 10/11] KVM: arm64: selftests: Import automatic system register definition generation from kernel Jing Zhang
2023-08-21 21:22 ` [PATCH v9 11/11] KVM: arm64: selftests: Test for setting ID register from usersapce Jing Zhang
2023-08-23 7:37 ` [PATCH v9 00/11] Enable writable for idregs DFR0,PFR0, MMFR{0,1,2,3} Cornelia Huck
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