From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C9F3EE4993 for ; Tue, 22 Aug 2023 09:49:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=l3ymAZxkYtLHHCJstZnpZYNNp6e071st0LrnPxykwsM=; b=zRflnyEtl9LBoI 12nMCUSBAZ038IkfkbgeyxNXwX4SoPfufF3YlJqXb4giopeJe7Xwnw1jeJZ0B1yrbkdL3ayuHLbuO 2OkAOjzuOiGpLZK45kUPvD1+5p0YVI22FIaeB1OwGvIHO9yZs/n3d00cnV0sbhbksre5oORTo8FlR O7+4UuueNXsdcjZ46bOvFw3k/h0gJlPUkGqAwqc1q0M+WLgXFO8kBeHVia2JFJC5DA3EHHYbUiXX0 EMnm+AAWaEeElHxH0mAK427pXR1CvVE38M2BVzno6iKqGwMhyRmCjzwasPWG8Br1+eLBxmNIOOtx8 8pmpWGq3vMlxxiJcD7Qw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYO0Y-00FZmm-34; Tue, 22 Aug 2023 09:49:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYO0V-00FZm0-0u; Tue, 22 Aug 2023 09:49:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A5BD011FB; Tue, 22 Aug 2023 02:49:40 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 54A3B3F64C; Tue, 22 Aug 2023 02:48:57 -0700 (PDT) Date: Tue, 22 Aug 2023 10:48:54 +0100 From: Andre Przywara To: Aleksandr Shubin Cc: linux-kernel@vger.kernel.org, Thierry Reding , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH v5 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Message-ID: <20230822104854.1fa5f1aa@donnerap.manchester.arm.com> In-Reply-To: <20230814133238.741950-2-privatesub2@gmail.com> References: <20230814133238.741950-1-privatesub2@gmail.com> <20230814133238.741950-2-privatesub2@gmail.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_024903_421940_F2471865 X-CRM114-Status: GOOD ( 22.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 14 Aug 2023 16:32:16 +0300 Aleksandr Shubin wrote: Hi Aleksandr, > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > The D1 and T113 are identical in terms of peripherals, > they differ only in the architecture of the CPU core, and > even share the majority of their DT. Because of that, > using the same compatible makes sense. > The R329 is a different SoC though, and should have > a different compatible string added, especially as there > is a difference in the number of channels. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > Add a device tree binding for them. > > Signed-off-by: Aleksandr Shubin > --- > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > new file mode 100644 > index 000000000000..9512d4bed322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner D1, T113-S3 and R329 PWM > + > +maintainers: > + - Aleksandr Shubin > + > +properties: > + compatible: > + oneOf: > + - const: allwinner,sun20i-d1-pwm > + - items: > + - const: allwinner,sun20i-r329-pwm > + - const: allwinner,sun20i-d1-pwm > + > + reg: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > + clocks: > + items: > + - description: 24 MHz oscillator > + - description: Bus Clock The manual tells me that the new PWMs can also use APB0 as the input clock, which (finally!) allows PWM frequencies above 24 MHz. So we should have an explicit reference to that clock - even if the bus clock happens to be gated version of APB0. Cheers, Andre > + > + clock-names: > + items: > + - const: hosc > + - const: bus > + > + resets: > + maxItems: 1 > + > + allwinner,pwm-channels: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The number of PWM channels configured for this instance > + enum: [6, 9] > + > +allOf: > + - $ref: pwm.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: allwinner,sun20i-r329-pwm > + > + then: > + required: > + - allwinner,pwm-channels > + > + else: > + properties: > + allwinner,pwm-channels: false > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - "#pwm-cells" > + - clocks > + - clock-names > + - resets > + > +examples: > + - | > + #include > + #include > + > + pwm: pwm@2000c00 { > + compatible = "allwinner,sun20i-d1-pwm"; > + reg = <0x02000c00 0x400>; > + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; > + clock-names = "hosc", "bus"; > + resets = <&ccu RST_BUS_PWM>; > + #pwm-cells = <0x3>; > + }; > + > +... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel