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From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Srinivas Goud <srinivas.goud@amd.com>
Cc: wg@grandegger.com, davem@davemloft.net, edumazet@google.com,
	kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	p.zabel@pengutronix.de, git@amd.com, michal.simek@amd.com,
	linux-can@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, appana.durga.rao@xilinx.com,
	naga.sureshkumar.relli@xilinx.com
Subject: Re: [PATCH v4 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors
Date: Mon, 4 Sep 2023 17:22:20 +0200	[thread overview]
Message-ID: <20230904-unbiased-putt-a1a2919b02c7-mkl@pengutronix.de> (raw)
In-Reply-To: <1693557645-2728466-4-git-send-email-srinivas.goud@amd.com>


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On 01.09.2023 14:10:45, Srinivas Goud wrote:
> Add ethtool stats interface for reading FIFO 1bit/2bit
> ECC errors information.
> 
> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
> ---
> Changes in v4:
> None
> 
> Changes in v3:
> None
> 
> Changes in v2:
> Add ethtool stats interface
> 
>  drivers/net/can/xilinx_can.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
> index 798b32b..50e0c9d 100644
> --- a/drivers/net/can/xilinx_can.c
> +++ b/drivers/net/can/xilinx_can.c
> @@ -219,6 +219,7 @@ struct xcan_devtype_data {
>   * @transceiver:		Optional pointer to associated CAN transceiver
>   * @rstc:			Pointer to reset control
>   * @ecc_enable:			ECC enable flag
> + * @stats_lock:			Lock for synchronizing hardware stats

To be precise: The lock is about the access of the 64 bit variables not
about the hardware access:
"Lock for accessing the "ecc_*bit_*fifo_cnt" stats"

>   * @ecc_2bit_rxfifo_cnt:	RXFIFO 2bit ECC count
>   * @ecc_1bit_rxfifo_cnt:	RXFIFO 1bit ECC count
>   * @ecc_2bit_txolfifo_cnt:	TXOLFIFO 2bit ECC count
> @@ -245,6 +246,7 @@ struct xcan_priv {
>  	struct phy *transceiver;
>  	struct reset_control *rstc;
>  	bool ecc_enable;
> +	spinlock_t stats_lock; /* Lock for synchronizing hardware stats */
>  	u64 ecc_2bit_rxfifo_cnt;
>  	u64 ecc_1bit_rxfifo_cnt;
>  	u64 ecc_2bit_txolfifo_cnt;
> @@ -1164,6 +1166,9 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
>  
>  	if (priv->ecc_enable) {
>  		u32 reg_ecc;
> +		unsigned long flags;

nitpick: move the flags before the reg_ecc.

> +
> +		spin_lock_irqsave(&priv->stats_lock, flags);
>  
>  		reg_ecc = priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET);
>  		if (isr & XCAN_IXR_E2BERX_MASK) {
> @@ -1212,6 +1217,8 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
>  		 */
>  		priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK |
>  				XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK);
> +
> +		spin_unlock_irqrestore(&priv->stats_lock, flags);
>  	}
>  
>  	if (cf.can_id) {
> @@ -1639,6 +1646,23 @@ static int xcan_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv)
>  	return 0;
>  }
>  
> +static void ethtool_get_ethtool_stats(struct net_device *ndev,
> +				      struct ethtool_stats *stats, u64 *data)
> +{
> +	struct xcan_priv *priv = netdev_priv(ndev);
> +	unsigned long flags;
> +	int i = 0;
> +
> +	spin_lock_irqsave(&priv->stats_lock, flags);
> +	data[i++] = priv->ecc_2bit_rxfifo_cnt;
> +	data[i++] = priv->ecc_1bit_rxfifo_cnt;
> +	data[i++] = priv->ecc_2bit_txolfifo_cnt;
> +	data[i++] = priv->ecc_1bit_txolfifo_cnt;
> +	data[i++] = priv->ecc_2bit_txtlfifo_cnt;
> +	data[i++] = priv->ecc_1bit_txtlfifo_cnt;
> +	spin_unlock_irqrestore(&priv->stats_lock, flags);
> +}
> +
>  static const struct net_device_ops xcan_netdev_ops = {
>  	.ndo_open	= xcan_open,
>  	.ndo_stop	= xcan_close,
> @@ -1648,6 +1672,7 @@ static const struct net_device_ops xcan_netdev_ops = {
>  
>  static const struct ethtool_ops xcan_ethtool_ops = {
>  	.get_ts_info = ethtool_op_get_ts_info,
> +	.get_ethtool_stats = ethtool_get_ethtool_stats,

You also should implement .get_strings and .get_sset_count. Have you
tested your patch with "ethtool -S can0"?

>  };
>  
>  /**
> -- 
> 2.1.1
> 
> 

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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_______________________________________________
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  reply	other threads:[~2023-09-04 15:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-01  8:40 [PATCH v4 0/3] can: xilinx_can: Add ECC feature support Srinivas Goud
2023-09-01  8:40 ` [PATCH v4 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc' Srinivas Goud
2023-09-04 14:52   ` Marc Kleine-Budde
2023-09-01  8:40 ` [PATCH v4 2/3] can: xilinx_can: Add ECC support Srinivas Goud
2023-09-04 15:04   ` Marc Kleine-Budde
2023-09-01  8:40 ` [PATCH v4 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Srinivas Goud
2023-09-04 15:22   ` Marc Kleine-Budde [this message]
2023-09-12  6:37   ` Marc Kleine-Budde

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