From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 353DCC83F2C for ; Tue, 5 Sep 2023 10:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ddd8AvHMj+U3fXPZlzTcGN63wDnQ3UkSR9KG7BiZ2uY=; b=pH58C7VstvcYN3 Bg6pcm9weSoctfaCmGYgx3RtBJWzcN2OtvV88n/+ua4LlrvS9ti7uG3u4RPYWG1MAknqvd12r9a/l 6v1gdEuSCymNkCROwaI/uVlTNBwy0/wRvrwkGKbRwohVW5H86+GanRfUWhoVRWBiXln8D6tbrPSmd 89DtTpprnrh8zRW3dM9PtJzeMBb5KJhyTzImCKjG6z8AxlMU6xlrW6uRXhFCcF96FWiIkEU2YDMTr fR3CgMmJgz22/qQfHIyW2kooBtWV76zfUEAhkRGpzC7jwcZvYA18ve+d65IwZwrsrQM91xhyPKGyQ Nf2UAHaezLXMkjPazC5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdTam-005qwn-1z; Tue, 05 Sep 2023 10:47:32 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdTak-005qwS-22 for linux-arm-kernel@lists.infradead.org; Tue, 05 Sep 2023 10:47:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8DEED60670; Tue, 5 Sep 2023 10:47:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7864DC433C7; Tue, 5 Sep 2023 10:47:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910849; bh=s7bezVMuronD8AnPMbbw+I84vvlIIOq2qxIuhKy2z2Q=; h=From:To:Cc:Subject:Date:From; b=PWOY0VLH5P7VHEKlqoZ4BQJC+35/X8ZmeCcrhJAZn/3qJC8XM8pwMkR6jmbHOzU3i z0qGV3eNLjPfHrwvdC1uC9USBmbEAJFiomM8Ma8Nb5wwrugycNcfhwdV0BPdSEvQ61 VoNlzCUuO4c98ykWC+h3igiQHUg/cobnCyc3FAfuMyigSdlw+WYbBVPsWXJyfqt7L9 9rCMxKu20XhCAyD+Ki9CTeevl1vwd5HOg5+KPZF2EW+MNinKl2JisRWKb/aAKNAERl p3n0pac9B0+VCKgvYO8+Of+gibWwcY3hsNdgAVDXEswkmFh5WujV2igUxcOBq0Rd38 osxnuGvI5hapQ== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Robin Murphy , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH 0/2] irqchip/gic-v3: Enable non-coherent GIC designs probing Date: Tue, 5 Sep 2023 12:47:19 +0200 Message-Id: <20230905104721.52199-1-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_034730_735750_ACA1A6EF X-CRM114-Status: GOOD ( 12.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GICv3 architecture specifications provide a means for the system programmer to set the shareability and cacheability attributes the GIC components (redistributors and ITSes) use to drive memory transactions. Albeit the architecture give control over shareability/cacheability memory transactions attributes (and barriers), it is allowed to connect the GIC interconnect ports to non-coherent memory ports on the interconnect, basically tying off shareability/cacheability "wires" and de-facto making the redistributors and ITSes non-coherent memory observers. This series aims at starting a discussion over a possible solution to this problem, by adding to the GIC device tree bindings the standard dma-noncoherent property. The GIC driver uses the property to force the redistributors and ITSes shareability attributes to non-shareable, which consequently forces the driver to use CMOs on GIC memory tables. On ARM DT DMA is default non-coherent, so the GIC driver can't rely on the generic DT dma-coherent/non-coherent property management layer (of_dma_is_coherent()) which would default all GIC designs in the field as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. When a consistent approach is agreed upon for DT an equivalent binding will be put forward for ACPI based systems. Lorenzo Pieralisi (2): dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property irqchip/gic-v3: Enable non-coherent redistributors/ITSes probing .../interrupt-controller/arm,gic-v3.yaml | 8 ++++++++ drivers/irqchip/irq-gic-v3-its.c | 19 +++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel