From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2006DCA0EC6 for ; Tue, 12 Sep 2023 00:29:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SYA1C9XdAwFPzDiKOv0VUrbgkZ9lOsnqBjhbtrnGKiA=; b=jTuE1IvskcAfD5 QaI+bVKuBw94pV5+sqKmeOwVpUwi0FkmYijfBWE8nOkYU8SKBxEboEEeCjy8NtcPEFepJEOVqCLx8 UHuKSxttTAl7VEB9Q8jKo3Ab6P7ak7MgzmppCrrprJnY75UZcZxCHMxKkb4hHR10RfUjaqivZhAD3 Dx41KhfLskWGODOnKuJ6j8j78QGs6aaLIKiYvhZq0xCo/kATWg5TSZxgXQZenQULI25X6gO7GOcHg a3YgUIZmi1/8e5dVVFAX7vrZIGa7F/IxKG99+Qn4W2LnI5+JeJzT3RJnmEOILzDxSxdR2hz7wUyQ4 GnYUTsIWLbf3SoSrnj7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qfrGc-001fuR-2m; Tue, 12 Sep 2023 00:28:34 +0000 Received: from mgamail.intel.com ([134.134.136.31]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qfrGa-001ftj-0V for linux-arm-kernel@lists.infradead.org; Tue, 12 Sep 2023 00:28:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694478512; x=1726014512; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=P6aSw8Is7RAGGaHzgqtzz8Glx5EKeJbVQPOjs9s6ppE=; b=gaZCMjCKBRBkVNJuUKTHEVCtm59GRPP1zi31eD6OdBv2lQHR8yqnvNKJ wMUA1bKpaHuFsHsFKkOpsn+UmmaRbMIid0cqH2KqPvZsibT9jucwfXMB0 HlkTn0ZWmSdX3AXUvYuLqHaxZRpBXT7fngMi8VNdQolStHYrTDsBKqjD2 dZpkkj9P7RTxOl+52U8cgvrOwI3HsOl4L6o1z+3M6wteAbrJUcAdssIWn r+GATiHwBX+Itam4OcwSxomyo9r6Xi5xh/jp94oQk1SYnfYDkmZMJNH1+ MdQHf+Ma+NTcpRptI6pjtAruPLEJ1BrK0H5tCQCPCjdOIGpkOnu+6vqmz A==; X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="442255223" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="442255223" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2023 17:28:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="772789070" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="772789070" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2023 17:28:29 -0700 Date: Mon, 11 Sep 2023 17:30:47 -0700 From: Ricardo Neri To: Radu Rendec Cc: Sudeep Holla , x86@kernel.org, Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Srinivas Pandruvada , Will Deacon , Zhang Rui , stable@vger.kernel.org, Ricardo Neri , "Ravi V. Shankar" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 1/3] cacheinfo: Allocate memory for memory if not done from the primary CPU Message-ID: <20230912003047.GA16425@ranerica-svr.sc.intel.com> References: <20230805012421.7002-1-ricardo.neri-calderon@linux.intel.com> <20230805012421.7002-2-ricardo.neri-calderon@linux.intel.com> <20230830114918.be4mvwfogdqmsxk6@bogus> <23a1677c3df233c220df68ea429a2d0fec52e1d4.camel@redhat.com> <20230830154707.dyeihenolc5nwmi2@bogus> <03e51c6072d80931a6b532ce1d4d7388a6f84d32.camel@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <03e51c6072d80931a6b532ce1d4d7388a6f84d32.camel@redhat.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230911_172832_242470_381AD88D X-CRM114-Status: GOOD ( 45.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 30, 2023 at 12:45:22PM -0400, Radu Rendec wrote: > On Wed, 2023-08-30 at 16:47 +0100, Sudeep Holla wrote: > > On Wed, Aug 30, 2023 at 08:13:09AM -0400, Radu Rendec wrote: > > > On Wed, 2023-08-30 at 12:49 +0100, Sudeep Holla wrote: > > > > On Fri, Aug 04, 2023 at 06:24:19PM -0700, Ricardo Neri wrote: > > > > > Commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary= CPU") > > > > > adds functionality that architectures can use to optionally alloc= ate and > > > > > build cacheinfo early during boot. Commit 6539cffa9495 ("cacheinf= o: Add > > > > > arch specific early level initializer") lets secondary CPUs corre= ct (and > > > > > reallocate memory) cacheinfo data if needed. > > > > > = > > > > > If the early build functionality is not used and cacheinfo does n= ot need > > > > > correction, memory for cacheinfo is never allocated. x86 does not= use the > > > > > early build functionality. Consequently, during the cacheinfo CPU= hotplug > > > > > callback, last_level_cache_is_valid() attempts to dereference a N= ULL > > > > > pointer: > > > > > = > > > > > =A0=A0=A0=A0 BUG: kernel NULL pointer dereference, address: 00000= 00000000100 > > > > > =A0=A0=A0=A0 #PF: supervisor read access in kernel mode > > > > > =A0=A0=A0=A0 #PF: error_code(0x0000) - not present page > > > > > =A0=A0=A0=A0 PGD 0 P4D 0 > > > > > =A0=A0=A0=A0 Oops: 0000 [#1] PREEPMT SMP NOPTI > > > > > =A0=A0=A0=A0 CPU: 0 PID 19 Comm: cpuhp/0 Not tainted 6.4.0-rc2 #1 > > > > > =A0=A0=A0=A0 RIP: 0010: last_level_cache_is_valid+0x95/0xe0a > > > > > = > > > > > Allocate memory for cacheinfo during the cacheinfo CPU hotplug ca= llback if > > > > > not done earlier. > > > > > = > > > > > Cc: Andreas Herrmann > > > > > Cc: Catalin Marinas > > > > > Cc: Chen Yu > > > > > Cc: Len Brown > > > > > Cc: Radu Rendec > > > > > Cc: Pierre Gondois > > > > > Cc: Pu Wen > > > > > Cc: "Rafael J. Wysocki" > > > > > Cc: Sudeep Holla > > > > > Cc: Srinivas Pandruvada > > > > > Cc: Will Deacon > > > > > Cc: Zhang Rui > > > > > Cc: linux-arm-kernel@lists.infradead.org > > > > > Cc: stable@vger.kernel.org > > > > > Acked-by: Len Brown > > > > > Fixes: 6539cffa9495 ("cacheinfo: Add arch specific early level in= itializer") > > > > = > > > > Not sure if we strictly need this(details below), but I am fine eit= her way. > > > > = > > > > > Signed-off-by: Ricardo Neri > > > > > --- > > > > > The motivation for commit 5944ce092b97 was to prevent a BUG splat= in > > > > > PREEMPT_RT kernels during memory allocation. This splat is not ob= served on > > > > > x86 because the memory allocation for cacheinfo happens in > > > > > detect_cache_attributes() from the cacheinfo CPU hotplug callback. > > > > > = > > > > > The dereference of a NULL pointer is not observed today because > > > > > cache_leaves(cpu) is zero until after init_cache_level() is calle= d (also > > > > > during the CPU hotplug callback). Patch2 will set it earlier and = the NULL- > > > > > pointer dereference will be observed. > > > > = > > > > Right, this is the information I have been asking in the previous v= ersions. > > > > This clarifies a lot. The trigger is in the patch 2/3 which is why = it didn't > > > > make complete sense to me without it when you posted this patch ind= ependently. > > > > Thanks for posting it together and sorry for the delay(both reviewi= ng this > > > > and in understanding the issue). > > > > = > > > > Given the trigger for NULL pointer dereference is in 2/3, I am not = sure > > > > if it is really worth applying this to all the stable kernels with = the > > > > commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary C= PU"). > > > > That is the reason why I asked to drop fixes tag if you agree with = me. > > > > It is simple fix, so I am OK if you prefer to see that in the stabl= e kernels > > > > as well. > > > = > > > Thanks for reviewing, Sudeep. Since my previous commit 6539cffa9495 > > > ("cacheinfo: Add arch specific early level initializer") opens a door > > > for the NULL pointer dereference, I would sleep better at night if the > > > fix was included in the stable kernels :) But seriously, I am concern= ed > > > that with the fix applied in mainline and not in stable, something el= se > > > could be backported to the stable in the future, that could trigger t= he > > > NULL pointer dereference there. Ricardo's patch 2/3 is one way to > > > trigger it, but you never know what other patch lands in mainline in > > > the future that assumes it's safe to set the cache leaves earlier. > > > = > > = > > Fair enough. I agree with you, so please retain the fixes tag as is. > > Please work with x86 maintainers to get it merged along with other patc= hes. > > Let me know if you have other plans. > = > Thanks, Sudeep. Technically, these are Ricardo's patches, so I will let > him engage with the x86 maintainers and drive the integration work. But > the plan looks good to me, and I will stand by and offer any support > may be needed for the fix patch. Thank you very much Sudeep and Radu for your feedback and review! The x86 maintainers are in the To: field of this patchset. The patches apply cleanly on top of the latest tip/master, but not on the latest rework of the topology evaluation from Thomas. Then I am not sure when/if this patchset will be merged. Thanks and BR, Ricardo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel