From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Haibo Xu <haibo1.xu@intel.com>,
xiaobo55x@gmail.com, Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Sean Christopherson <seanjc@google.com>,
Ricardo Koller <ricarkol@google.com>,
Vishal Annapurve <vannapurve@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Vipin Sharma <vipinsh@google.com>,
David Matlack <dmatlack@google.com>,
Colton Lewis <coltonlewis@google.com>,
Aaron Lewis <aaronlewis@google.com>,
Thomas Huth <thuth@redhat.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
kvm@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v3 9/9] KVM: riscv: selftests: Add sstc timer test
Date: Thu, 14 Sep 2023 12:15:50 +0200 [thread overview]
Message-ID: <20230914-2232dea1c6d03fb5985755e6@orel> (raw)
In-Reply-To: <20230914-reflector-preshow-786425ad7ae2@wendy>
On Thu, Sep 14, 2023 at 10:52:15AM +0100, Conor Dooley wrote:
> On Thu, Sep 14, 2023 at 11:36:01AM +0200, Andrew Jones wrote:
> > > +static inline void cpu_relax(void)
> > > +{
> > > +#ifdef __riscv_zihintpause
> > > + asm volatile("pause" ::: "memory");
> > > +#else
> > > + /* Encoding of the pause instruction */
> > > + asm volatile(".4byte 0x100000F" ::: "memory");
> > > +#endif
> > > +}
> >
> > cpu_relax() should go to include/riscv/processor.h
>
> Can the one from asm/vdso/processor.h be reused, or are there special
> considerations preventing that?
We'd need to copy it into tools/arch/riscv/include/asm, but it could be
done. Hmm, now that I look at it, I see we're missing the barrier() call
in this kvm selftests version.
Thanks,
drew
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next prev parent reply other threads:[~2023-09-14 10:16 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 1:36 [PATCH v3 0/9] RISCV: Add kvm Sstc timer selftests Haibo Xu
2023-09-14 1:36 ` [PATCH v3 1/9] KVM: selftests: Unify the codes for guest exception handling Haibo Xu
2023-09-14 1:36 ` [PATCH v3 2/9] KVM: selftests: Unify the makefile rule for split targets Haibo Xu
2023-09-14 8:46 ` Andrew Jones
2023-10-03 10:28 ` Andrew Jones
2023-10-08 2:58 ` Haibo Xu
2023-11-22 8:13 ` Andrew Jones
2023-11-23 2:50 ` Haibo Xu
2023-09-14 1:36 ` [PATCH v3 3/9] KVM: arm64: selftests: Split arch_timer test code Haibo Xu
2023-09-14 8:43 ` Andrew Jones
2023-09-14 1:36 ` [PATCH v3 4/9] tools: riscv: Add header file csr.h Haibo Xu
2023-09-14 8:14 ` Andrew Jones
2023-09-15 6:08 ` Haibo Xu
2023-09-14 1:36 ` [PATCH v3 5/9] KVM: riscv: selftests: Switch to use macro from csr.h Haibo Xu
2023-09-14 8:52 ` Andrew Jones
2023-09-15 6:13 ` Haibo Xu
2023-09-14 1:37 ` [PATCH v3 6/9] KVM: riscv: selftests: Add exception handling support Haibo Xu
2023-09-14 1:37 ` [PATCH v3 7/9] KVM: riscv: selftests: Add guest helper to get vcpu id Haibo Xu
2023-09-14 1:37 ` [PATCH v3 8/9] KVM: riscv: selftests: Change vcpu_has_ext to a common function Haibo Xu
2023-09-14 9:05 ` Andrew Jones
2023-09-15 6:14 ` Haibo Xu
2023-09-14 1:37 ` [PATCH v3 9/9] KVM: riscv: selftests: Add sstc timer test Haibo Xu
2023-09-14 9:36 ` Andrew Jones
2023-09-14 9:52 ` Conor Dooley
2023-09-14 10:15 ` Andrew Jones [this message]
2023-09-15 6:23 ` Haibo Xu
2023-09-14 9:51 ` Andrew Jones
2023-09-15 6:21 ` Haibo Xu
2023-12-04 2:42 ` Haibo Xu
2023-12-04 11:32 ` Andrew Jones
2023-12-05 7:58 ` Haibo Xu
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