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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id k8-20020a5d5248000000b0031fc4c31d77sm1340310wrc.88.2023.09.14.03.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 03:15:51 -0700 (PDT) Date: Thu, 14 Sep 2023 12:15:50 +0200 From: Andrew Jones To: Conor Dooley Cc: Haibo Xu , xiaobo55x@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Sean Christopherson , Ricardo Koller , Vishal Annapurve , Vitaly Kuznetsov , Vipin Sharma , David Matlack , Colton Lewis , Aaron Lewis , Thomas Huth , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v3 9/9] KVM: riscv: selftests: Add sstc timer test Message-ID: <20230914-2232dea1c6d03fb5985755e6@orel> References: <64e0637cd6f22dd7557ed44bd2242001e7830d1c.1694421911.git.haibo1.xu@intel.com> <20230914-ee133dd5e804282ce28833d6@orel> <20230914-reflector-preshow-786425ad7ae2@wendy> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230914-reflector-preshow-786425ad7ae2@wendy> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230914_031557_553931_11148971 X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 14, 2023 at 10:52:15AM +0100, Conor Dooley wrote: > On Thu, Sep 14, 2023 at 11:36:01AM +0200, Andrew Jones wrote: > > > +static inline void cpu_relax(void) > > > +{ > > > +#ifdef __riscv_zihintpause > > > + asm volatile("pause" ::: "memory"); > > > +#else > > > + /* Encoding of the pause instruction */ > > > + asm volatile(".4byte 0x100000F" ::: "memory"); > > > +#endif > > > +} > > > > cpu_relax() should go to include/riscv/processor.h > > Can the one from asm/vdso/processor.h be reused, or are there special > considerations preventing that? We'd need to copy it into tools/arch/riscv/include/asm, but it could be done. Hmm, now that I look at it, I see we're missing the barrier() call in this kvm selftests version. Thanks, drew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel