From: Hsiao Chien Sung <shawn.sung@mediatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Chen-Yu Tsai <wenst@chromium.org>, CK Hu <ck.hu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Hsiao Chien Sung <shawn.sung@mediatek.com>
Subject: [PATCH v2 01/11] soc: mediatek: Add register definitions for GCE
Date: Mon, 18 Sep 2023 16:41:57 +0800 [thread overview]
Message-ID: <20230918084207.23604-2-shawn.sung@mediatek.com> (raw)
In-Reply-To: <20230918084207.23604-1-shawn.sung@mediatek.com>
Add register definitions for GCE so users can use them
as a buffer to store data.
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
include/linux/soc/mediatek/mtk-cmdq.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 649955d2cf5c..a253c001c861 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -14,6 +14,16 @@
#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))
#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))
+/*
+ * Every cmdq thread has its own SPRs (Specific Purpose Registers),
+ * so there are 4 * 24 (threads) = 96 SPRs in GCE that shares the
+ * same indexes below
+ */
+#define CMDQ_THR_SPR_IDX0 (0)
+#define CMDQ_THR_SPR_IDX1 (1)
+#define CMDQ_THR_SPR_IDX2 (2)
+#define CMDQ_THR_SPR_IDX3 (3)
+
struct cmdq_pkt;
struct cmdq_client_reg {
--
2.18.0
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next prev parent reply other threads:[~2023-09-18 8:42 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-18 8:41 [PATCH v2 00/11] Support IGT in display driver Hsiao Chien Sung
2023-09-18 8:41 ` Hsiao Chien Sung [this message]
2023-09-18 9:06 ` [PATCH v2 01/11] soc: mediatek: Add register definitions for GCE AngeloGioacchino Del Regno
2023-09-18 8:41 ` [PATCH v2 02/11] soc: mediatek: Support GCE jump to absolute Hsiao Chien Sung
2023-09-18 8:51 ` CK Hu (胡俊光)
2023-09-18 8:41 ` [PATCH v2 03/11] soc: mediatek: Disable 9-bit alpha in ETHDR Hsiao Chien Sung
2023-09-18 9:06 ` AngeloGioacchino Del Regno
2023-09-18 8:42 ` [PATCH v2 04/11] drm/mediatek: Add OVL compatible name for MT8195 Hsiao Chien Sung
2023-09-18 9:09 ` CK Hu (胡俊光)
2023-09-18 9:21 ` AngeloGioacchino Del Regno
2023-09-18 9:27 ` CK Hu (胡俊光)
2023-10-11 9:38 ` Shawn Sung (宋孝謙)
2023-10-11 11:51 ` AngeloGioacchino Del Regno
2023-10-12 2:18 ` Shawn Sung (宋孝謙)
2023-09-18 8:42 ` [PATCH v2 05/11] drm/mediatek: Adjust DRM mode configs for IGT Hsiao Chien Sung
2023-09-18 9:05 ` CK Hu (胡俊光)
2023-09-18 8:42 ` [PATCH v2 06/11] drm/mediatek: Support alpha blending in display driver Hsiao Chien Sung
2023-09-18 9:25 ` CK Hu (胡俊光)
2023-09-18 8:42 ` [PATCH v2 07/11] drm/mediatek: Support alpha blending in VDOSYS0 Hsiao Chien Sung
2023-09-18 8:42 ` [PATCH v2 08/11] drm/mediatek: Support alpha blending in VDOSYS1 Hsiao Chien Sung
2023-09-18 8:42 ` [PATCH v2 09/11] drm/mediatek: Support CRC in display driver Hsiao Chien Sung
2023-09-18 8:42 ` [PATCH v2 10/11] drm/mediatek: Support CRC in VDOSYS0 Hsiao Chien Sung
2023-09-18 8:42 ` [PATCH v2 11/11] drm/mediatek: Support CRC in VDOSYS1 Hsiao Chien Sung
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