[PATCH] ARM: Fix typo and misinformation in ARM page table documentation

[PATCH] ARM: Fix typo and misinformation in ARM page table documentation

[Ariel Gorovoy]

The documentation in the file is comprehensive and explains
that there is an offset of 2048 bytes betwen the linux PTE
and the hardware PTE.
However, the comment I changed remarked that there is actually
a 1024 byte offset, which is incorrect as I understand it.

Also fixed a typo ("transation"->"translation").

Fixes: 17f5721 ("ARM: 7075/1: LPAE: Factor out 2-level page table definitions into sep…")
Signed-off-by: Ariel Gorovoy <arielgori@gmail.com>
---
 arch/arm/include/asm/pgtable-2level.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index ce543cd9380c..a1d19da4ff6a 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -63,7 +63,7 @@
  *
  * However, when the "young" bit is cleared, we deny access to the page
  * by clearing the hardware PTE.  Currently Linux does not flush the TLB
- * for us in this case, which means the TLB will retain the transation
+ * for us in this case, which means the TLB will retain the translation
  * until either the TLB entry is evicted under pressure, or a context
  * switch which changes the user space mapping occurs.
  */
@@ -114,7 +114,7 @@
  * bits.
  *
  * The PTE table pointer refers to the hardware entries; the "Linux"
- * entries are stored 1024 bytes below.
+ * entries are stored 2048 bytes below.
  */
 #define L_PTE_VALID		(_AT(pteval_t, 1) << 0)		/* Valid */
 #define L_PTE_PRESENT		(_AT(pteval_t, 1) << 0)
-- 
2.34.1


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