From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6710ACD4F49 for ; Fri, 22 Sep 2023 10:26:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2GXs9HzpopHQmY+L7SqYKB8Z2b+q+F5j0faovAIYo58=; b=DgYEKUVQxOLghG jcwI4H/xV8WnHhk8yX4YXDOTMTwojor0ZEo1uMMgve/pwV36C+wRqFb8TrVPwZnygkwPxOjXe43qw ryVPFqaX9kkbkmhqm0x8ZzKKfY7Q77yWgp9uZr1JUBjU3N4Dz+ysGdjHXUltCdFShKzjq2Gz21/iF 6yg73pabhpF6x+HPGm6Z1PxSDBA5nNXDCe8j7IvoCpDCpMSe5JM9F3bFN2wBbabClpcGKg06RciJU b3i8wdYFPrkUNAa/cxuwU7mSvgg7c037hiwBb6GQ1C1fkS/qdeBYNWss5/e0KM7Gn9Ha7hmn2ekbF IuhtPwZk0gzguaMpqIBg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjdLx-008pVW-1g; Fri, 22 Sep 2023 10:25:41 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjdLu-008pT6-2x for linux-arm-kernel@lists.infradead.org; Fri, 22 Sep 2023 10:25:40 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D5B0D6225A; Fri, 22 Sep 2023 10:25:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A588C433C8; Fri, 22 Sep 2023 10:25:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695378337; bh=Wc3oGik2b3xC60zZ2thLAcrs3gO0rhT5suSF1Jz39N8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=E9doIbNLN7pl6noXB9KJPXotrmbmEhfBvBfpv+hiH8U0Xe1IVHmm1s8QkpYLd+5A4 YQay4xzPJ18XCibiYMMuTWgF1EzBRU+k8s9CJhlLc2O3By9L0f8z9oQO8E1rlMy2TO WuiAnw8tmGS7quhhzfNJDCbNhndvCMUzxYB5390OlKcTmWrvH5DUCZDWwuY1rBQJ6l 8/pJw1ty32NOPYYdMD2n1T6/YI8dhXeg36lpMIl+1dfASaa2KhU8QALWc/a9Ce63am 3Llrp9HzVo3v2TB5G0FH02quiThBee8Q/g4w8Ou1AUxa20f7HhFmDuNKs5fLDIZ1LG pWas8X7y9Q2fQ== Date: Fri, 22 Sep 2023 11:25:31 +0100 From: Will Deacon To: Oliver Upton Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , linux-arm-kernel@lists.infradead.org, Gavin Shan Subject: Re: [PATCH 1/2] arm64: tlbflush: Rename MAX_TLBI_OPS Message-ID: <20230922102531.GA22838@willie-the-truck> References: <20230920080133.944717-1-oliver.upton@linux.dev> <20230920080133.944717-2-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230920080133.944717-2-oliver.upton@linux.dev> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230922_032539_020250_90F49350 X-CRM114-Status: GOOD ( 19.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 20, 2023 at 08:01:32AM +0000, Oliver Upton wrote: > Perhaps unsurprisingly, I-cache invalidations suffer from performance > issues similar to TLB invalidations on certain systems. TLB and I-cache > maintenance all result in DVM on the mesh, which is where the real > bottleneck lies. > > Rename the heuristic to point the finger at DVM, such that it may be > reused for limiting I-cache invalidations. > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/tlbflush.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index b149cf9f91bc..3431d37e5054 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -333,7 +333,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) > * This is meant to avoid soft lock-ups on large TLB flushing ranges and not > * necessarily a performance improvement. > */ > -#define MAX_TLBI_OPS PTRS_PER_PTE > +#define MAX_DVM_OPS PTRS_PER_PTE > > /* > * __flush_tlb_range_op - Perform TLBI operation upon a range > @@ -413,12 +413,12 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, > > /* > * When not uses TLB range ops, we can handle up to > - * (MAX_TLBI_OPS - 1) pages; > + * (MAX_DVM_OPS - 1) pages; > * When uses TLB range ops, we can handle up to > * (MAX_TLBI_RANGE_PAGES - 1) pages. > */ > if ((!system_supports_tlb_range() && > - (end - start) >= (MAX_TLBI_OPS * stride)) || > + (end - start) >= (MAX_DVM_OPS * stride)) || > pages >= MAX_TLBI_RANGE_PAGES) { > flush_tlb_mm(vma->vm_mm); > return; > @@ -451,7 +451,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end > { > unsigned long addr; > > - if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) { > + if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) { > flush_tlb_all(); > return; > } > -- > 2.42.0.459.ge4e396fd5e-goog Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel