[PATCH v4 0/5] Update of phyBOARD-Pollux-i.MX8MP

[PATCH v4 0/5] Update of phyBOARD-Pollux-i.MX8MP

[Cem Tenruh]

Updates for the phyCORE-i.MX8MP and phyBOARD-Pollux-i.MX8MP devicetrees.
This adds CAN-FD, RS232/RS485 and USB support for phyBOARD-Pollux-i.MX8MP.
This also adds gpio-line-name properties.

Changes in v4:
 - split previous (arm64: dts: imx8mp: Add gpio-line-names Patch 3/4)
   into two patches (Patch 3/5) & (Patch 4/5)
 - Updated commit header & message (Patch 3/5)
 - Added missing signed-off (Patch 2/5) & (Patch 5/5)

Changes in v3:
 - removed "regulator-always-on" protperty (Patch 2/4)

Changes in v2:
 - Edited commit message (Patch 4/4)
 - Added comment to UART2 node (Patch 4/4)

Cem Tenruh (2):
  arm64: dts: imx8mp-phycore-som: Add gpio-line-names
  arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names

Teresa Remmet (3):
  arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
  arm64: dts: imx8mp-phyboard-pollux: Enable USB support
  arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485

 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 154 ++++++++++++++++++
 .../dts/freescale/imx8mp-phycore-som.dtsi     |  13 ++
 2 files changed, 167 insertions(+)

-- 
2.25.1


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[PATCH v4 1/5] arm64: dts: imx8mp-phyboard-pollux: Add flexcan support

[Cem Tenruh]

From: Teresa Remmet <t.remmet@phytec.de>

Add flexcan1 and flexcan2 support for CAN FD on phyBOARD-Pollux.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
Changes in v4:
 - No changes

Changes in v3:
 - No changes

Changes in v2:
 - No changes
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 1e14c4cd3128..1750fadb64c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -19,6 +19,26 @@ chosen {
 		stdout-path = &uart1;
 	};
 
+	reg_can1_stby: regulator-can1-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan1_reg>;
+		gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can1-stby";
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan2_reg>;
+		gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can2-stby";
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -57,6 +77,21 @@ ethphy0: ethernet-phy@1 {
 	};
 };
 
+/* CAN FD */
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_stby>;
+	status = "okay";
+};
+
 &i2c2 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default", "gpio";
@@ -136,6 +171,32 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
 		>;
 	};
 
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154
+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
+		>;
+	};
+
+	pinctrl_flexcan1_reg: flexcan1reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x154
+		>;
+	};
+
+	pinctrl_flexcan2_reg: flexcan2reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x154
+		>;
+	};
+
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
-- 
2.25.1


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[PATCH v4 2/5] arm64: dts: imx8mp-phyboard-pollux: Enable USB support

[Cem Tenruh]

From: Teresa Remmet <t.remmet@phytec.de>

Enable USB support for both interfaces in host mode.
USB1 is directly conncted to a type-A connector and USB2
is attached to a 4-Port USB Hub.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
Changes in v4:
 - Added my missing "signed-off-by"

Changes in v3:
 - Removed "regulator-always-on" protperty

Changes in v2:
 - No changes
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 1750fadb64c3..494a40077d16 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -39,6 +39,16 @@ reg_can2_stby: regulator-can2-stby {
 		regulator-name = "can2-stby";
 	};
 
+	reg_usb1_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_vbus>;
+		gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb1_host_vbus";
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -136,6 +146,37 @@ &uart1 {
 	status = "okay";
 };
 
+/* USB1 Host mode Type-A */
+&usb3_phy0 {
+	vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB */
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	fsl,permanently-attached;
+	fsl,disable-port-power-control;
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
 /* SD-Card */
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
@@ -224,6 +265,12 @@ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x40
 		>;
 	};
 
+	pinctrl_usb1_vbus: usb1vbusgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x10
+		>;
+	};
+
 	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
-- 
2.25.1


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[PATCH v4 3/5] arm64: dts: imx8mp-phycore-som: Add gpio-line-names

[Cem Tenruh]

Add gpio-line-names to the imx8mp-phycore-som devicetree.

Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
---
Changes in v4:
 - Moved carrierboard gpio-line-names to seperate patch
 - Updated commit header & message

Changes in v3:
 - No changes

Changes in v2:
 - No changes
---
 .../boot/dts/freescale/imx8mp-phycore-som.dtsi      | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index d8df97060e8f..c976c3b6cbc6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -199,6 +199,19 @@ &wdog1 {
 	status = "okay";
 };
 
+&gpio1 {
+	gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "X_nETHPHY_INT";
+};
+
+&gpio4 {
+	gpio-line-names = "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "X_PMIC_IRQ_B";
+};
+
 &iomuxc {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-- 
2.25.1


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[PATCH v4 4/5] arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names

[Cem Tenruh]

Add gpio-line-names to the imx8mp-phyboard-pollux devicetree.

Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
---
Changes in v4:
 - Added this new patch
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 494a40077d16..562d4fee2011 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -191,6 +191,33 @@ &usdhc2 {
 	status = "okay";
 };
 
+&gpio1 {
+	gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
+		"PMIC_SD_VSEL", "", "", "", "", "",
+		"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
+};
+
+&gpio2 {
+	gpio-line-names = "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "X_SD2_CD_B", "", "", "",
+		"", "", "", "SD2_RESET_B";
+};
+
+&gpio3 {
+	gpio-line-names = "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "", "", "nCAN1_EN", "nCAN2_EN";
+};
+
+&gpio4 {
+	gpio-line-names = "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "",
+		"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
+};
+
 &iomuxc {
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
-- 
2.25.1


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[PATCH v4 5/5] arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485

[Cem Tenruh]

From: Teresa Remmet <t.remmet@phytec.de>

Add UART2 for RS232/RS485 support.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
(Updated the node by not setting the reserved bits(BIT 0 and BIT 3)
and enabled internal pullup for RX and TX.)
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
Changes in v4:
 - Added my missing "signed-off-by"

Changes in v3:
 - No changes

Changes in v2:
 - Edited commit message
 - Added comment to UART2 node
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 562d4fee2011..c8640cac3edc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -177,6 +177,16 @@ &usb_dwc3_1 {
 	status = "okay";
 };
 
+/* RS232/RS485 */
+&uart2 {
+	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
 /* SD-Card */
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
@@ -298,6 +308,15 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x10
 		>;
 	};
 
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
+			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS	0x140
+			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS	0x140
+		>;
+	};
+
 	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
-- 
2.25.1


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Re: [PATCH v4 0/5] Update of phyBOARD-Pollux-i.MX8MP

[Shawn Guo]

On Wed, Sep 06, 2023 at 12:08:52PM +0200, Cem Tenruh wrote:
> Updates for the phyCORE-i.MX8MP and phyBOARD-Pollux-i.MX8MP devicetrees.
> This adds CAN-FD, RS232/RS485 and USB support for phyBOARD-Pollux-i.MX8MP.
> This also adds gpio-line-name properties.
> 
> Changes in v4:
>  - split previous (arm64: dts: imx8mp: Add gpio-line-names Patch 3/4)
>    into two patches (Patch 3/5) & (Patch 4/5)
>  - Updated commit header & message (Patch 3/5)
>  - Added missing signed-off (Patch 2/5) & (Patch 5/5)
> 
> Changes in v3:
>  - removed "regulator-always-on" protperty (Patch 2/4)
> 
> Changes in v2:
>  - Edited commit message (Patch 4/4)
>  - Added comment to UART2 node (Patch 4/4)
> 
> Cem Tenruh (2):
>   arm64: dts: imx8mp-phycore-som: Add gpio-line-names
>   arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names
> 
> Teresa Remmet (3):
>   arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
>   arm64: dts: imx8mp-phyboard-pollux: Enable USB support
>   arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485

Applied all, thanks!

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