Re: [PATCH v2 07/28] clk: renesas: rzg2l: add support for RZ/G3S PLL

Geert Uytterhoeven
2023-10-04T08:45:50Z

On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add support for reading the frequency of PLL1/4/6 available on RZ/G3S.
> The computation formula for PLL frequency is as follows:
> Fout = (nir + nfr / 4096) * Fin / (mr * pr)
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v2:
> - added GENMASK() defines for DIV_P, DIV_M, DIV_NI, DIV_NF
> - used mul_u64_u32_shr() as suggested by Geert on v1
> - s/CLK_TYPE_G3S_SAM_PLL/CLK_TYPE_G3S_PLL/g

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

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when I'm talking to journalists I just say "programmer" or something like that.
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