[PATCH v2 08/28] clk: renesas: rzg2l: add struct clk_hw_data

Claudiu
2023-09-29T05:40:36Z

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add clk_hw_data struct that keeps the core part of a clock data. The
sd_hw_data embeds a member of type struct clk_hw_data along with other
members (in the next commits). This commit prepares the field for
refactoring the SD MUX clock driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

Changes in v2:
- collected tags

drivers/clk/renesas/rzg2l-cpg.c | 52 +++++++++++++++++++++------------
1 file changed, 34 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 02058a2d39ca..ac05463d1d98 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -63,13 +63,29 @@

#define MAX_VCLK_FREQ (148500000)

-struct sd_hw_data {
+/**
+ * struct clk_hw_data - clock hardware data
+ * @hw: clock hw
+ * @conf: clock configuration (register offset, shift, width)
+ * @priv: CPG private data structure
+ */
+struct clk_hw_data {
struct clk_hw hw;
u32 conf;
struct rzg2l_cpg_priv *priv;
};

-#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw)
+#define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw)
+
+/**
+ * struct sd_hw_data - SD clock hardware data
+ * @hw_data: clock hw data
+ */
+struct sd_hw_data {
+ struct clk_hw_data hw_data;
+};
+
+#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data)

struct rzg2l_pll5_param {
u32 pl5_fracin;
@@ -188,10 +204,10 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,

static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
- struct sd_hw_data *hwdata = to_sd_hw_data(hw);
- struct rzg2l_cpg_priv *priv = hwdata->priv;
- u32 off = GET_REG_OFFSET(hwdata->conf);
- u32 shift = GET_SHIFT(hwdata->conf);
+ struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
+ u32 off = GET_REG_OFFSET(clk_hw_data->conf);
+ u32 shift = GET_SHIFT(clk_hw_data->conf);
const u32 clk_src_266 = 2;
u32 msk, val, bitmask;
unsigned long flags;
@@ -208,7 +224,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
* The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and
* the index to value mapping is done by adding 1 to the index.
*/
- bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+ bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16;
msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
spin_lock_irqsave(&priv->rmw_lock, flags);
if (index != clk_src_266) {
@@ -237,12 +253,12 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)

static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
{
- struct sd_hw_data *hwdata = to_sd_hw_data(hw);
- struct rzg2l_cpg_priv *priv = hwdata->priv;
- u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));
+ struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
+ u32 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));

- val >>= GET_SHIFT(hwdata->conf);
- val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
+ val >>= GET_SHIFT(clk_hw_data->conf);
+ val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);

return val ? val - 1 : 0;
}
@@ -258,17 +274,17 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
- struct sd_hw_data *clk_hw_data;
+ struct sd_hw_data *sd_hw_data;
struct clk_init_data init;
struct clk_hw *clk_hw;
int ret;

- clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
- if (!clk_hw_data)
+ sd_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL);
+ if (!sd_hw_data)
return ERR_PTR(-ENOMEM);

- clk_hw_data->priv = priv;
- clk_hw_data->conf = core->conf;
+ sd_hw_data->hw_data.priv = priv;
+ sd_hw_data->hw_data.conf = core->conf;

init.name = core->name;
init.ops = &rzg2l_cpg_sd_clk_mux_ops;
@@ -276,7 +292,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
init.num_parents = core->num_parents;
init.parent_names = core->parent_names;

- clk_hw = &clk_hw_data->hw;
+ clk_hw = &sd_hw_data->hw_data.hw;
clk_hw->init = &init;

ret = devm_clk_hw_register(priv->dev, clk_hw);
--
2.39.2