From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF32FE77362 for ; Sat, 30 Sep 2023 09:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7V4OojquUWmClFRqpmOqhZu1Nr31x9HaOf+JbGSCdHU=; b=VP4qVMX6G+1eXkV8ZM8bQKl5Pg u8m3kwRrBQft3E4gnzlhyRM3c63piR4e7GxBwztu9YJ0Fq2Gd0xwJBfABy2H0rDx8QoLwpqZSwVgY BLjY8GpOA0sndEG7LHCm86ovNiMYTQ9nBrYGp3BtyGfx2bAHmfZ6XBYXAycA2vuEtH9LzJyxaZzRe Ub5t7i2PAB11vRYa95FTkmwJv3topjthXsUIvcJOAR9/CubgiRlFQ5LTDJ/X+uSdNVoHgPLLpHaFZ omY3lvYzKMERup/f5WaQUrauMawj3iNzHVxnIInZ/DF5NSq8nWYk30d2Lqr7xAeNTdegG/IWalBfZ Lirz4g5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qmWJ4-009Ey0-1g; Sat, 30 Sep 2023 09:30:38 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qmWJ1-009ExO-0i for linux-arm-kernel@lists.infradead.org; Sat, 30 Sep 2023 09:30:37 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 94B45B80765; Sat, 30 Sep 2023 09:30:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E4FFC433C7; Sat, 30 Sep 2023 09:30:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696066232; bh=tin0U19Nf4ANHDkcJXK1cl2YnmWbZlWUAWYQns6q95A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GrJMGkZXrPIT7StjOmeW+Fl8xwgebNyjtUdAOXRb7MJ/TkKMz13DPx5Qoi0HwXWp1 Mj2c9yfx7SVQvUXsKfnq2P+RHMAyI6mccAk8fKyDW4gULxhlZPGShSX0WB+iPaLSr7 mUiK0T0ddtqYsPPd0h1y920r2619heC5HkItOvuIA5vB7ZbXGsO9h6OwebpZKIXYfF cpzqp4c9klicbTpjXdFyqmWoSxM1g9gXG3Rv/6g0U6gQbBYq5kpvOkn71X4pJA4cJz KBit/mnJ2hHesyHyAhpoqwuKWDve8VIIRBfPJ7YgW7vnqnXZCqNQXymd7meZ+Cwm2y ZlR+A2h8PKMfg== Date: Sat, 30 Sep 2023 10:30:24 +0100 From: Conor Dooley To: Duje =?utf-8?Q?Mihanovi=C4=87?= Cc: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de, balejk@matfyz.cz Subject: Re: [PATCH RESEND v5 3/8] dt-bindings: clock: Add Marvell PXA1908 clock bindings Message-ID: <20230930-purr-catchable-7149ee271df9@spud> References: <20230929-pxa1908-lkml-v5-0-5aa5a1109c5f@skole.hr> <20230929-pxa1908-lkml-v5-3-5aa5a1109c5f@skole.hr> MIME-Version: 1.0 In-Reply-To: <20230929-pxa1908-lkml-v5-3-5aa5a1109c5f@skole.hr> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230930_023035_554171_74AD7C42 X-CRM114-Status: GOOD ( 18.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0338454338395703187==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0338454338395703187== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xztbYI3ipS2Vh9bj" Content-Disposition: inline --xztbYI3ipS2Vh9bj Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 29, 2023 at 05:41:59PM +0200, Duje Mihanovi=C4=87 wrote: > Add dt bindings and documentation for the Marvell PXA1908 clock > controller. >=20 > Signed-off-by: Duje Mihanovi=C4=87 Reviewed-by: Conor Dooley Thanks, Conor. > --- > .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ > include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++= ++++++ > 2 files changed, 136 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml= b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml > new file mode 100644 > index 000000000000..4e78933232b6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Marvell PXA1908 Clock Controllers > + > +maintainers: > + - Duje Mihanovi=C4=87 > + > +description: | > + The PXA1908 clock subsystem generates and supplies clock to various > + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock > + controller blocks, with the ones currently supported being APBC, APBCP= , MPMU > + and APMU roughly corresponding to internal buses. > + > + All these clock identifiers could be found in . > + > +properties: > + compatible: > + enum: > + - marvell,pxa1908-apbc > + - marvell,pxa1908-apbcp > + - marvell,pxa1908-mpmu > + - marvell,pxa1908-apmu > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + # APMU block: > + - | > + clock-controller@d4282800 { > + compatible =3D "marvell,pxa1908-apmu"; > + reg =3D <0xd4282800 0x400>; > + #clock-cells =3D <1>; > + }; > diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bin= dings/clock/marvell,pxa1908.h > new file mode 100644 > index 000000000000..fb15b0d0cd4c > --- /dev/null > +++ b/include/dt-bindings/clock/marvell,pxa1908.h > @@ -0,0 +1,88 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H > +#define __DTS_MARVELL_PXA1908_CLOCK_H > + > +/* plls */ > +#define PXA1908_CLK_CLK32 1 > +#define PXA1908_CLK_VCTCXO 2 > +#define PXA1908_CLK_PLL1_624 3 > +#define PXA1908_CLK_PLL1_416 4 > +#define PXA1908_CLK_PLL1_499 5 > +#define PXA1908_CLK_PLL1_832 6 > +#define PXA1908_CLK_PLL1_1248 7 > +#define PXA1908_CLK_PLL1_D2 8 > +#define PXA1908_CLK_PLL1_D4 9 > +#define PXA1908_CLK_PLL1_D8 10 > +#define PXA1908_CLK_PLL1_D16 11 > +#define PXA1908_CLK_PLL1_D6 12 > +#define PXA1908_CLK_PLL1_D12 13 > +#define PXA1908_CLK_PLL1_D24 14 > +#define PXA1908_CLK_PLL1_D48 15 > +#define PXA1908_CLK_PLL1_D96 16 > +#define PXA1908_CLK_PLL1_D13 17 > +#define PXA1908_CLK_PLL1_32 18 > +#define PXA1908_CLK_PLL1_208 19 > +#define PXA1908_CLK_PLL1_117 20 > +#define PXA1908_CLK_PLL1_416_GATE 21 > +#define PXA1908_CLK_PLL1_624_GATE 22 > +#define PXA1908_CLK_PLL1_832_GATE 23 > +#define PXA1908_CLK_PLL1_1248_GATE 24 > +#define PXA1908_CLK_PLL1_D2_GATE 25 > +#define PXA1908_CLK_PLL1_499_EN 26 > +#define PXA1908_CLK_PLL2VCO 27 > +#define PXA1908_CLK_PLL2 28 > +#define PXA1908_CLK_PLL2P 29 > +#define PXA1908_CLK_PLL2VCODIV3 30 > +#define PXA1908_CLK_PLL3VCO 31 > +#define PXA1908_CLK_PLL3 32 > +#define PXA1908_CLK_PLL3P 33 > +#define PXA1908_CLK_PLL3VCODIV3 34 > +#define PXA1908_CLK_PLL4VCO 35 > +#define PXA1908_CLK_PLL4 36 > +#define PXA1908_CLK_PLL4P 37 > +#define PXA1908_CLK_PLL4VCODIV3 38 > + > +/* apb (apbc) peripherals */ > +#define PXA1908_CLK_UART0 1 > +#define PXA1908_CLK_UART1 2 > +#define PXA1908_CLK_GPIO 3 > +#define PXA1908_CLK_PWM0 4 > +#define PXA1908_CLK_PWM1 5 > +#define PXA1908_CLK_PWM2 6 > +#define PXA1908_CLK_PWM3 7 > +#define PXA1908_CLK_SSP0 8 > +#define PXA1908_CLK_SSP1 9 > +#define PXA1908_CLK_IPC_RST 10 > +#define PXA1908_CLK_RTC 11 > +#define PXA1908_CLK_TWSI0 12 > +#define PXA1908_CLK_KPC 13 > +#define PXA1908_CLK_SWJTAG 14 > +#define PXA1908_CLK_SSP2 15 > +#define PXA1908_CLK_TWSI1 16 > +#define PXA1908_CLK_THERMAL 17 > +#define PXA1908_CLK_TWSI3 18 > + > +/* apb (apbcp) peripherals */ > +#define PXA1908_CLK_UART2 1 > +#define PXA1908_CLK_TWSI2 2 > +#define PXA1908_CLK_AICER 3 > + > +/* axi (apmu) peripherals */ > +#define PXA1908_CLK_CCIC1 1 > +#define PXA1908_CLK_ISP 2 > +#define PXA1908_CLK_DSI1 3 > +#define PXA1908_CLK_DISP1 4 > +#define PXA1908_CLK_CCIC0 5 > +#define PXA1908_CLK_SDH0 6 > +#define PXA1908_CLK_SDH1 7 > +#define PXA1908_CLK_USB 8 > +#define PXA1908_CLK_NF 9 > +#define PXA1908_CLK_CORE_DEBUG 10 > +#define PXA1908_CLK_VPU 11 > +#define PXA1908_CLK_GC 12 > +#define PXA1908_CLK_SDH2 13 > +#define PXA1908_CLK_GC2D 14 > +#define PXA1908_CLK_TRACE 15 > +#define PXA1908_CLK_DVC_DFC_DEBUG 16 > + > +#endif >=20 > --=20 > 2.42.0 >=20 >=20 --xztbYI3ipS2Vh9bj Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZRfqsAAKCRB4tDGHoIJi 0jIyAQClD4BtPUpM5qBMvLM7SmIKbmSXy1dLhn3+zWj1ceg1kgD/XLaUdvmI7W0U Itc9gfrWaDvaBLCZSGLLCFp10gm07AE= =eaix -----END PGP SIGNATURE----- --xztbYI3ipS2Vh9bj-- --===============0338454338395703187== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0338454338395703187==--