From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDDB4E81DF6 for ; Fri, 6 Oct 2023 13:00:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kQhYMZHYsfbOZ4WevyA8sJqUsEKlKWhNiaevUufMSUE=; b=ku34CXDPEQyfpr HGsbuvy0JC2er3FHLvYvBOe34gWvRq218QK4d2aUoVPyWG5NZMtN0CLCTNvp7WTkLoKXhcgjOX+8d eJCbuIZbS3W8AnJOzwdB4oXHSwctZ87i0492oUSI0Md15idB0aSvUKXdfMojKnQM//MvxgH9g0KI9 WbdN2bY1SAzdar/KAy8v8OH5vRP7Fb+PzAnz+KSfv7sYiekT5EnVDeDf8my7j4bN0w6G2CCehOYmq gskS2v+P/2bhNyJbfZK4PXbErBltTw66LWlO7OaBFJAdc6UseRSFu759tZHqfKuGAjDFoVKrV5sIn Pz7LKtEuGzyTR1qcwQZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qokQl-005pjI-14; Fri, 06 Oct 2023 12:59:47 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qokQf-005pgT-1u for linux-arm-kernel@lists.infradead.org; Fri, 06 Oct 2023 12:59:43 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id E934F61D57; Fri, 6 Oct 2023 12:59:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBA64C433CC; Fri, 6 Oct 2023 12:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696597180; bh=iOWyeF/KRwGpiqZfKpX3chHM50vO4O6sz4uB89KKvbU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m1zaLxvxNrq/JKivnpB19VtMWfwwpgXr53MZ4plq4TD5Lv6tqCzOQzjEtI4kwUqq9 fW9g2+YNXBj8Tty4Pki+pG/9Jr8ruf+WVYddCHdV/Hifx/TM9Cii+EpmmhEDz7rJZx LYzmf6m0uPyOYlNJKDDO1E/NCl+NVWMDWaovub0H+a0q34H6WFgiF8EM5VABHOiZVy gM6FYvgiS3HA/9XVKi8XNo8w0ePseSOejkcZyPPFC+uu1LCPfzMVPjtLhOZIxx38SP tVysBsxR2fxYfEtuv6Bvr5+kB27ShcKNgWyghtZM8zMHgXGh3rDNtTJE6ytlKLa1tM T9CikPZ4LOCIQ== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, Mark Rutland , Robin Murphy , "Rafael J. Wysocki" , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH v3 1/5] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property Date: Fri, 6 Oct 2023 14:59:25 +0200 Message-Id: <20231006125929.48591-2-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231006125929.48591-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> <20231006125929.48591-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231006_055941_672550_DD99BA65 X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent. Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU. Reviewed-by: Rob Herring Signed-off-by: Lorenzo Pieralisi Cc: Rob Herring --- .../bindings/interrupt-controller/arm,gic-v3.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 2bc38479a41e..0f4a062c9d6f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -106,6 +106,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: + Present if the GIC redistributors permit programming shareability + and cacheability attributes but are connected to a non-coherent + downstream interconnect. + msi-controller: description: Only present if the Message Based Interrupt functionality is @@ -193,6 +199,12 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: + Present if the GIC ITS permits programming shareability and + cacheability attributes but is connected to a non-coherent + downstream interconnect. + msi-controller: true "#msi-cells": -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel