From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B41ECDB47E for ; Fri, 13 Oct 2023 10:23:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o3pXSiAxU+AfCgCEHOqPNrzZ3wckVM6qY+oc//31510=; b=f1Xi8NU5pDHh8G r7EZXmP71L+3Y4jnQXZjSCliRa1SD46UelNw8/3py6HGGwG04sCpny15xlu9U4/qr7DXqONUiaSf0 w6xbabWeb7lZLj5OhypUIhhnqhHlpQBOv3BB7RkydohSRBR6rC4pjq1sFpyHhIMg5LP8f3NfbUw94 w6jemcUCbUK2kML5+VUUC9f/rSg8UtbdPvvQ4pdsJF5IfHKULzys9GNgFG0/0sIo3Xfoklpdwa7fU xPx6NgLkBpqdkLqwqtsTCcZjTBgGB9gO/u+P+5dyJSG5Yt/I2yl+gJYLQl6rRogcV/wVp9X1aL7zT F8JLlDmz0DsHfskk3qAw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qrFKF-0033Mf-2d; Fri, 13 Oct 2023 10:23:23 +0000 Received: from relay5-d.mail.gandi.net ([217.70.183.197]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qrFKB-0033L3-1O for linux-arm-kernel@lists.infradead.org; Fri, 13 Oct 2023 10:23:22 +0000 Received: by mail.gandi.net (Postfix) with ESMTPSA id 78AAF1C000C; Fri, 13 Oct 2023 10:23:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1697192593; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=grez1VavYsE8MeA1IyNendydX2wgr+/XkRXEEiQMhPE=; b=P4TYh65Ey9FWFljdN827vHBiv82oNaQU/KwHOC6ExB4/2CkCywQqA9G0nK5m1r6M8A0w5t 31KHkEzInug/HgPxlrhRXycEapLG1EU/pAGcQMWK3IwfZoyzo8OJxAnGDSvphPUPQAd8dR NeMxmgn0ApO5EdzG7YVY0sEMdCUqDHp2IKPyAtN2Z6jWIa0hfGIiyzqUcCM60JnutakDaD 2WdcuFozW3PLuLXkVL5O91zmt59qEIq/pAun2Bq3Axxgb85/3IvCWQ6FdYDd39LVa1weXE mVTfQvusuRMk+1unUQ4kQega5iBvATGTkeSB//6arL9sUF4YAj9jGwOxYNKbDA== Date: Fri, 13 Oct 2023 12:23:11 +0200 From: Alexandre Belloni To: Ronald Wahl Subject: Re: [RESEND][PATCH] clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware Message-ID: <20231013102311929c3fab@mail.local> References: <20231007161803.31342-1-rwahl@gmx.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231007161803.31342-1-rwahl@gmx.de> X-GND-Sasl: alexandre.belloni@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231013_032319_633474_01E58E75 X-CRM114-Status: GOOD ( 27.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Lezcano , Claudiu Beznea , linux-kernel@vger.kernel.org, Ronald Wahl , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 07/10/2023 18:17:13+0200, Ronald Wahl wrote: > From: Ronald Wahl > > On SAM9 hardware two cascaded 16 bit timers are used to form a 32 bit > high resolution timer that is used as scheduler clock when the kernel > has been configured that way (CONFIG_ATMEL_CLOCKSOURCE_TCB). > > The driver initially triggers a reset-to-zero of the two timers but this > reset is only performed on the next rising clock. For the first timer > this is ok - it will be in the next 60ns (16MHz clock). For the chained > second timer this will only happen after the first timer overflows, i.e. > after 2^16 clocks (~4ms with a 16MHz clock). So with other words the > scheduler clock resets to 0 after the first 2^16 clock cycles. > > It looks like that the scheduler does not like this and behaves wrongly > over its lifetime, e.g. some tasks are scheduled with a long delay. Why > that is and if there are additional requirements for this behaviour has > not been further analysed. > > There is a simple fix for resetting the second timer as well when the > first timer is reset and this is to set the ATMEL_TC_ASWTRG_SET bit in > the Channel Mode register (CMR) of the first timer. This will also rise > the TIOA line (clock input of the second timer) when a software trigger > respective SYNC is issued. > > Signed-off-by: Ronald Wahl Acked-by: Alexandre Belloni > --- > drivers/clocksource/timer-atmel-tcb.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c > index 27af17c99590..2a90c92a9182 100644 > --- a/drivers/clocksource/timer-atmel-tcb.c > +++ b/drivers/clocksource/timer-atmel-tcb.c > @@ -315,6 +315,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) > writel(mck_divisor_idx /* likely divide-by-8 */ > | ATMEL_TC_WAVE > | ATMEL_TC_WAVESEL_UP /* free-run */ > + | ATMEL_TC_ASWTRG_SET /* TIOA0 rises at software trigger */ > | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ > | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ > tcaddr + ATMEL_TC_REG(0, CMR)); > -- > 2.41.0 > -- Alexandre Belloni, co-owner and COO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel