From: Jason Gunthorpe <jgg@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org,
Robin Murphy <robin.murphy@arm.com>,
Michael Shavit <mshavit@google.com>,
Nicolin Chen <nicolinc@nvidia.com>
Subject: Re: [PATCH 01/19] iommu/arm-smmu-v3: Add a type for the STE
Date: Fri, 13 Oct 2023 11:00:28 -0300 [thread overview]
Message-ID: <20231013140028.GA352534@nvidia.com> (raw)
In-Reply-To: <20231013103734.GA13594@willie-the-truck>
On Fri, Oct 13, 2023 at 11:37:35AM +0100, Will Deacon wrote:
> > -static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
> > +static struct arm_smmu_ste *
> > +arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
> > {
> > - __le64 *step;
> > struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
> >
> > if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
> > - struct arm_smmu_strtab_l1_desc *l1_desc;
> > int idx;
> >
> > /* Two-level walk */
> > idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
> > - l1_desc = &cfg->l1_desc[idx];
> > - idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS;
> > - step = &l1_desc->l2ptr[idx];
> > + return &cfg->l1_desc[idx].l2ptr[sid & ((1 << STRTAB_SPLIT) - 1)];
> > } else {
> > /* Simple linear lookup */
> > - step = &cfg->strtab[sid * STRTAB_STE_DWORDS];
> > + return (struct arm_smmu_ste *)&cfg
> > + ->strtab[sid * STRTAB_STE_DWORDS];
>
> Why not change the type of 'struct arm_smmu_strtab_cfg::strtab' at the same
> time?
It doesn't always point at a STE.
arm_smmu_init_strtab_2lvl() sets strtab to:
l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,
GFP_KERNEL);
cfg->strtab = strtab;
And arm_smmu_init_strtab_linear() sets strtab to:
size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3);
strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma,
GFP_KERNEL);
cfg->strtab = strtab;
I can add this patch if you like immediately after:
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index d5ba85034c1386..bdb559878615b8 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1559,7 +1559,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
return 0;
size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3);
- strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];
+ strtab = &cfg->strtab.l1_desc[sid >> STRTAB_SPLIT];
desc->span = STRTAB_SPLIT + 1;
desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma,
@@ -2347,8 +2347,7 @@ arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
return &cfg->l1_desc[idx].l2ptr[sid & ((1 << STRTAB_SPLIT) - 1)];
} else {
/* Simple linear lookup */
- return (struct arm_smmu_ste *)&cfg
- ->strtab[sid * STRTAB_STE_DWORDS];
+ return &cfg->strtab.linear[sid * STRTAB_STE_DWORDS];
}
}
@@ -3421,17 +3420,15 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
{
unsigned int i;
struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
- void *strtab = smmu->strtab_cfg.strtab;
cfg->l1_desc = devm_kcalloc(smmu->dev, cfg->num_l1_ents,
sizeof(*cfg->l1_desc), GFP_KERNEL);
if (!cfg->l1_desc)
return -ENOMEM;
- for (i = 0; i < cfg->num_l1_ents; ++i) {
- arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);
- strtab += STRTAB_L1_DESC_DWORDS << 3;
- }
+ for (i = 0; i < cfg->num_l1_ents; ++i)
+ arm_smmu_write_strtab_l1_desc(
+ &smmu->strtab_cfg.strtab.l1_desc[i], &cfg->l1_desc[i]);
return 0;
}
@@ -3463,7 +3460,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
l1size);
return -ENOMEM;
}
- cfg->strtab = strtab;
+ cfg->strtab.l1_desc = strtab;
/* Configure strtab_base_cfg for 2 levels */
reg = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_2LVL);
@@ -3490,7 +3487,7 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
size);
return -ENOMEM;
}
- cfg->strtab = strtab;
+ cfg->strtab.linear = strtab;
cfg->num_l1_ents = 1 << smmu->sid_bits;
/* Configure strtab_base_cfg for a linear table covering all SIDs */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 74f6f9e28c6e84..6d75adb1a72b4f 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -620,7 +620,10 @@ struct arm_smmu_s2_cfg {
};
struct arm_smmu_strtab_cfg {
- __le64 *strtab;
+ union {
+ struct arm_smmu_ste *linear;
+ __le64 *l1_desc;
+ } strtab;
dma_addr_t strtab_dma;
struct arm_smmu_strtab_l1_desc *l1_desc;
unsigned int num_l1_ents;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-10-13 14:01 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 0:33 [PATCH 00/19] Update SMMUv3 to the modern iommu API (part 1/2) Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 01/19] iommu/arm-smmu-v3: Add a type for the STE Jason Gunthorpe
2023-10-13 10:37 ` Will Deacon
2023-10-13 14:00 ` Jason Gunthorpe [this message]
2023-10-11 0:33 ` [PATCH 02/19] iommu/arm-smmu-v3: Master cannot be NULL in arm_smmu_write_strtab_ent() Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 03/19] iommu/arm-smmu-v3: Remove ARM_SMMU_DOMAIN_NESTED Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 04/19] iommu/arm-smmu-v3: Make STE programming independent of the callers Jason Gunthorpe
2023-10-12 8:10 ` Michael Shavit
2023-10-12 12:16 ` Jason Gunthorpe
2023-10-18 11:05 ` Michael Shavit
2023-10-18 13:04 ` Jason Gunthorpe
2023-10-20 8:23 ` Michael Shavit
2023-10-20 11:39 ` Jason Gunthorpe
2023-10-23 8:36 ` Michael Shavit
2023-10-23 12:05 ` Jason Gunthorpe
2023-12-15 20:26 ` Michael Shavit
2023-12-17 13:03 ` Jason Gunthorpe
2023-12-18 12:35 ` Michael Shavit
2023-12-18 12:42 ` Michael Shavit
2023-12-19 13:42 ` Michael Shavit
2023-12-25 12:17 ` Michael Shavit
2023-12-25 12:58 ` Michael Shavit
2023-12-27 15:33 ` Jason Gunthorpe
2023-12-27 15:46 ` Jason Gunthorpe
2024-01-02 8:08 ` Michael Shavit
2024-01-02 14:48 ` Jason Gunthorpe
2024-01-03 16:52 ` Michael Shavit
2024-01-03 17:50 ` Jason Gunthorpe
2024-01-06 8:36 ` [PATCH] " Michael Shavit
2024-01-06 8:36 ` [PATCH] iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry_step() Michael Shavit
2024-01-10 13:34 ` Jason Gunthorpe
2024-01-06 8:36 ` [PATCH] iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_entry Michael Shavit
2024-01-12 16:36 ` Jason Gunthorpe
2024-01-16 9:23 ` Michael Shavit
2024-01-10 13:10 ` [PATCH] iommu/arm-smmu-v3: Make STE programming independent of the callers Jason Gunthorpe
2024-01-06 8:50 ` [PATCH 04/19] " Michael Shavit
2024-01-12 19:45 ` Jason Gunthorpe
2024-01-03 15:42 ` Michael Shavit
2024-01-03 15:49 ` Jason Gunthorpe
2024-01-03 16:47 ` Michael Shavit
2024-01-02 8:13 ` Michael Shavit
2024-01-02 14:48 ` Jason Gunthorpe
2023-10-18 10:54 ` Michael Shavit
2023-10-18 12:24 ` Jason Gunthorpe
2023-10-19 23:03 ` Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 05/19] iommu/arm-smmu-v3: Consolidate the STE generation for abort/bypass Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 06/19] iommu/arm-smmu-v3: Move arm_smmu_rmr_install_bypass_ste() Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 07/19] iommu/arm-smmu-v3: Move the STE generation for S1 and S2 domains into functions Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 08/19] iommu/arm-smmu-v3: Build the whole STE in arm_smmu_make_s2_domain_ste() Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 09/19] iommu/arm-smmu-v3: Hold arm_smmu_asid_lock during all of attach_dev Jason Gunthorpe
2023-10-24 2:44 ` Michael Shavit
2023-10-24 2:48 ` Michael Shavit
2023-10-24 11:50 ` Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 10/19] iommu/arm-smmu-v3: Compute the STE only once for each master Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 11/19] iommu/arm-smmu-v3: Do not change the STE twice during arm_smmu_attach_dev() Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 12/19] iommu/arm-smmu-v3: Put writing the context descriptor in the right order Jason Gunthorpe
2023-10-12 9:01 ` Michael Shavit
2023-10-12 12:34 ` Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 13/19] iommu/arm-smmu-v3: Pass smmu_domain to arm_enable/disable_ats() Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 14/19] iommu/arm-smmu-v3: Remove arm_smmu_master->domain Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 15/19] iommu/arm-smmu-v3: Add a global static IDENTITY domain Jason Gunthorpe
2023-10-18 11:06 ` Michael Shavit
2023-10-18 12:26 ` Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 16/19] iommu/arm-smmu-v3: Add a global static BLOCKED domain Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 17/19] iommu/arm-smmu-v3: Use the identity/blocked domain during release Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 18/19] iommu/arm-smmu-v3: Pass arm_smmu_domain and arm_smmu_device to finalize Jason Gunthorpe
2023-10-11 0:33 ` [PATCH 19/19] iommu/arm-smmu-v3: Convert to domain_alloc_paging() Jason Gunthorpe
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231013140028.GA352534@nvidia.com \
--to=jgg@nvidia.com \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=mshavit@google.com \
--cc=nicolinc@nvidia.com \
--cc=robin.murphy@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).