From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E30A0CDB47E for ; Fri, 13 Oct 2023 16:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=gTCY5NjJjvOpVEZeZifLFsAwZeVLHP/JpqD7skkXrUU=; b=Axvr0+pcS9eiRv OIYK4twYnLXbYD7sYQ9OYNlGd+NV8p/Mz8Mqw8h1vyovWFIGvkc0sCcFQ4sd91wzRXa3Za3BwuHhN KEXjfQ6aMOdVWYa/bpCd8Jh9HNcw/nzW+B/KlfpXf+O4YIXqrnyYA69MHzp/mu/Y9qefiRRe249HK JKGq4Bc0UOQckeUroV/CFhR9MAUKk7bHxOo66WYo4vww5Y1XfaGYV5JI1C32p1GASUzn7Ths9bmrq nNSlMhpi2IgXxDwxHKq5Im2xXFrCmPqLbw2f1/DvbZ2xSyWepMoi7eFnt1C0cvc1UMUW9BF9pfmMe pF23ZoCD1Sot/quzpTRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qrL3Z-003s6Q-0J; Fri, 13 Oct 2023 16:30:33 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qrL3W-003s5h-01 for linux-arm-kernel@lists.infradead.org; Fri, 13 Oct 2023 16:30:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 1884CCE3073; Fri, 13 Oct 2023 16:30:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 109A7C433C8; Fri, 13 Oct 2023 16:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697214627; bh=vh4TnsBJPXKkBZ4qGrkc49O31rDOcZhRMhVj+HGI4BY=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=gviA7DdGJ83WDBASoN7ICKgep7rh2loHKxb5ZbwFtgn7zllg0pzEIh6pMoj1tyMr3 4UUeA1TeUgH4Af1srPOkIn6Gnnxy8hxGKJE7T8wQ4XtvxgWp42Lc+dFdrSeFP71b2/ CUCF3yQJSy6yXXzelSQcbbM4sLtJrLiZWin8Hfjg7mngS8XRN4vXy8CxagAG27gAHH 0MDMHdtHU8YCb6qpeeLvrs/6OQkr8dt4a4Xkucdzh1wZiPqFEb/t2gIC+1OOYTvrlT N/ZrRnhtMCsXpDS+KBAr4VSBqlt1QOchk8svklSkIJmUoiTwR3TKGJT0SQZLSp95u4 WUtS6hzwCy+4Q== Date: Fri, 13 Oct 2023 11:30:25 -0500 From: Bjorn Helgaas To: Shuai Xue Cc: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, renyu.zj@linux.alibaba.com Subject: Re: [PATCH v7 3/4] drivers/perf: add DesignWare PCIe PMU driver Message-ID: <20231013163025.GA1116248@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231013_093030_417664_5B07F1A3 X-CRM114-Status: GOOD ( 26.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 13, 2023 at 11:46:44AM +0800, Shuai Xue wrote: > > > On 2023/10/13 00:25, Bjorn Helgaas wrote: > > On Thu, Oct 12, 2023 at 11:28:55AM +0800, Shuai Xue wrote: > >> This commit adds the PCIe Performance Monitoring Unit (PMU) driver support > >> for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express > >> Core controller IP which provides statistics feature. The PMU is not a PCIe > >> Root Complex integrated End Point(RCiEP) device but only register counters > >> provided by each PCIe Root Port. IIUC, the PMU is directly integrated into the Root Port: it's discovered and operated via the Root Port config space. If so, I wouldn't bother mentioning RCiEP because there's no need to list all the things it's *not*. > >> To facilitate collection of statistics the controller provides the > >> following two features for each Root Port: > >> > >> - Time Based Analysis (RX/TX data throughput and time spent in each > >> low-power LTSSM state) > >> - Event counters (Error and Non-Error for lanes) > >> > >> Note, only one counter for each type and does not overflow interrupt. > > > > Not sure what "does not overflow interrupt" means. Does it mean > > there's no interrupt generated when the counter overflows? > > Yes, exactly. The rootport does NOT generate interrupt when the > couter overflows. I think the assumption hidden in this design is > 64-bit counter will not overflow within observable time. > > PCIe 5.0 slots can now reach anywhere between ~4GB/sec for a x1 slot > up to ~64GB/sec for a x16 slot. The unit of counter is 16 byte. > > 2^64/(64/16*10^9)/60/60/24/365=146 years > > so, the counter will not overflow within 146 years. Certainly a reasonable assumption :) But I'm confused about how many counters there are. Clearly there are two features ((1) time-based analysis and (2) event counters). "One counter for each type" suggests there's one counter for time-based analysis and a second counter for event counting, but from dwc_pcie_pmu_event_add(), it looks like each Root Port might have a single counter, and you can decide whether that counter is used for time-based analysis or event counting, but you can't do both at the same time? And the event counting is for a single lane, not for the link as a whole? If so, I might word this as: Each Root Port contains one counter that can be used for either: - Time-Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) or - Event counting (error and non-error events for a specified lane) There is no interrupt for counter overflow. > >> + Enable perf support for Synopsys DesignWare PCIe PMU Performance > >> + monitoring event on platform including the Yitian 710. > > > > Should this mention Alibaba or T-Head? I don't know how > > Alibaba/T-Head/Yitian are all related. > > The server chips, named Yitian 710, are custom-built by Alibaba Group's chip > development business, T-Head. > > Enable perf support for Synopsys DesignWare PCIe PMU Performance > monitoring event on platform including the Alibaba Yitian 710. > > Is this okay? Perfect :) Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel