From: Hsiao Chien Sung <shawn.sung@mediatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
"CK Hu" <ck.hu@mediatek.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Fei Shao <fshao@chromium.org>, Sean Paul <sean@poorly.run>,
Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Moudy Ho <moudy.ho@mediatek.com>,
"Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
Nathan Lu <nathan.lu@mediatek.com>,
"Hsiao Chien Sung" <shawn.sung@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v8 15/23] drm/mediatek: Manage component's clock with function pointers
Date: Mon, 16 Oct 2023 18:40:02 +0800 [thread overview]
Message-ID: <20231016104010.3270-16-shawn.sung@mediatek.com> (raw)
In-Reply-To: <20231016104010.3270-1-shawn.sung@mediatek.com>
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 111 +++++++-----------
1 file changed, 44 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 60e5dfe9ef0d..fffef2a4f919 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -53,6 +53,7 @@ struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
enum mtk_ddp_comp_id comp_id;
int alias_id;
+ const struct mtk_ddp_comp_funcs *funcs;
};
struct mtk_disp_ovl_adaptor {
@@ -67,20 +68,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
};
+static const struct mtk_ddp_comp_funcs _ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _rdma = {
+ .clk_enable = mtk_mdp_rdma_clk_enable,
+ .clk_disable = mtk_mdp_rdma_clk_disable,
+};
+
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
- [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
- [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
- [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
- [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &_merge },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -186,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
int mtk_ovl_adaptor_clk_enable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
- int ret;
int i;
-
- for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- ret = pm_runtime_get_sync(comp);
- if (ret < 0) {
- dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
- goto pwr_err;
- }
- }
+ int ret;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0)
- ret = mtk_mdp_rdma_clk_enable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- ret = mtk_merge_clk_enable(comp);
- else
- ret = mtk_ethdr_clk_enable(comp);
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ ret = comp_matches[i].funcs->clk_enable(dev);
if (ret) {
- dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
- goto clk_err;
+ while (--i >= 0)
+ comp_matches[i].funcs->clk_disable(dev);
+ return ret;
}
}
-
- return ret;
-
-clk_err:
- while (--i >= 0) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- if (i < OVL_ADAPTOR_MERGE0)
- mtk_mdp_rdma_clk_disable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- mtk_merge_clk_disable(comp);
- else
- mtk_ethdr_clk_disable(comp);
- }
- i = OVL_ADAPTOR_MERGE0;
-
-pwr_err:
- while (--i >= 0)
- pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
-
- return ret;
+ return 0;
}
void mtk_ovl_adaptor_clk_disable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0) {
- mtk_mdp_rdma_clk_disable(comp);
- pm_runtime_put(comp);
- } else if (i < OVL_ADAPTOR_ETHDR0) {
- mtk_merge_clk_disable(comp);
- } else {
- mtk_ethdr_clk_disable(comp);
- }
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ comp_matches[i].funcs->clk_disable(dev);
}
}
--
2.18.0
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next prev parent reply other threads:[~2023-10-16 11:45 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 10:39 [PATCH v8 00/23] Add display driver for MT8188 VDOSYS1 Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 01/23] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 02/23] dt-bindings: display: mediatek: mdp-rdma: " Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 03/23] dt-bindings: display: mediatek: merge: " Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 04/23] dt-bindings: display: mediatek: padding: Add MT8188 Hsiao Chien Sung
2023-10-17 9:31 ` AngeloGioacchino Del Regno
2023-10-16 10:39 ` [PATCH v8 06/23] dt-bindings: reset: mt8188: Add VDOSYS reset control bits Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 07/23] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 08/23] soc: mediatek: Support MT8188 VDOSYS1 Padding " Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 09/23] soc: mediatek: Support reset bit mapping in mmsys driver Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 10/23] soc: mediatek: Add MT8188 VDOSYS reset bit map Hsiao Chien Sung
2023-10-16 10:39 ` [PATCH v8 11/23] drm/mediatek: Rename OVL_ADAPTOR_TYPE_RDMA Hsiao Chien Sung
2023-10-17 9:40 ` AngeloGioacchino Del Regno
2023-10-16 10:39 ` [PATCH v8 12/23] drm/mediatek: Refine device table of OVL adaptor Hsiao Chien Sung
2023-10-17 9:40 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 13/23] drm/mediatek: Sort OVL adaptor components Hsiao Chien Sung
2023-10-17 9:40 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 14/23] drm/mediatek: Add component ID to component match structure Hsiao Chien Sung
2023-10-17 9:40 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` Hsiao Chien Sung [this message]
2023-10-17 9:41 ` [PATCH v8 15/23] drm/mediatek: Manage component's clock with function pointers AngeloGioacchino Del Regno
2023-10-17 9:47 ` AngeloGioacchino Del Regno
2023-10-17 10:50 ` Shawn Sung (宋孝謙)
2023-10-17 11:57 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 16/23] drm/mediatek: Start/Stop components " Hsiao Chien Sung
2023-10-17 9:41 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 17/23] drm/mediatek: Support MT8188 Padding in display driver Hsiao Chien Sung
2023-10-17 9:36 ` CK Hu (胡俊光)
2023-10-17 9:44 ` AngeloGioacchino Del Regno
2023-10-17 11:17 ` Shawn Sung (宋孝謙)
2023-10-16 10:40 ` [PATCH v8 18/23] drm/mediatek: Add Padding to OVL adaptor Hsiao Chien Sung
2023-10-17 9:39 ` CK Hu (胡俊光)
2023-10-17 9:47 ` AngeloGioacchino Del Regno
2023-10-17 11:09 ` Shawn Sung (宋孝謙)
2023-10-16 10:40 ` [PATCH v8 19/23] drm/mediatek: Return error if MDP RDMA failed to enable the clock Hsiao Chien Sung
2023-10-17 9:48 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 20/23] drm/mediatek: Remove the redundant driver data for DPI Hsiao Chien Sung
2023-10-17 9:49 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 21/23] drm/mediatek: Fix underrun in VDO1 when switches off the layer Hsiao Chien Sung
2023-10-17 9:45 ` CK Hu (胡俊光)
2023-10-17 9:50 ` AngeloGioacchino Del Regno
2023-10-16 10:40 ` [PATCH v8 22/23] drm/mediatek: Power on devices in OVL adaptor when atomic enable Hsiao Chien Sung
2023-10-17 9:54 ` AngeloGioacchino Del Regno
2023-10-17 11:04 ` Shawn Sung (宋孝謙)
2023-10-18 2:02 ` CK Hu (胡俊光)
2023-10-18 4:54 ` Shawn Sung (宋孝謙)
2023-10-16 10:40 ` [PATCH v8 23/23] drm/mediatek: Support MT8188 VDOSYS1 in display driver Hsiao Chien Sung
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