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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id lb5-20020a05687c330500b001cc9bc7b569sm394499oac.27.2023.10.17.13.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 13:14:05 -0700 (PDT) Received: (nullmailer pid 2675575 invoked by uid 1000); Tue, 17 Oct 2023 20:14:04 -0000 Date: Tue, 17 Oct 2023 15:14:04 -0500 From: Rob Herring To: Frank Li Cc: miquel.raynal@bootlin.com, conor.culhane@silvaco.com, alexandre.belloni@bootlin.com, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, joe@perches.com, peng.fan@nxp.com, alexander.stein@ew.tq-group.com, haibo.chen@nxp.com, ping.bai@nxp.com, xiaoning.wang@nxp.com, sherry.sun@nxp.com, linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev Subject: Re: [PATCH 2/2] arm64: dts: freescale: imx93: add i3c1 and i3c2 Message-ID: <20231017201404.GA2570433-robh@kernel.org> References: <20231016152450.2850498-1-Frank.Li@nxp.com> <20231016152450.2850498-2-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231016152450.2850498-2-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_131411_454343_C78FB8E5 X-CRM114-Status: GOOD ( 13.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 16, 2023 at 11:24:50AM -0400, Frank Li wrote: > Add I3C1 and I3C2. > > Signed-off-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 26 ++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi > index 6f85a05ee7e1..4d9ed0b32853 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -242,6 +242,19 @@ tpm2: pwm@44320000 { > status = "disabled"; > }; > > + i3c1: i3c-master@44330000 { > + compatible = "silvaco,i3c-master"; The real problem here is not whether we have "v1" or not, but you need an SoC specific compatible. Unless there's a public spec where we can know exactly how many resets, clocks, interrupts, etc. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel