[PATCH v2] PCI: keystone: Fix ks_pcie_v3_65_add_bus() for AM654x SoC

From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
	<bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <r-gunasekaran@ti.com>,
	<srk@ti.com>, <s-vadapalli@ti.com>
Subject: [PATCH v2] PCI: keystone: Fix ks_pcie_v3_65_add_bus() for AM654x SoC
Date: Wed, 18 Oct 2023 13:20:38 +0530	[thread overview]
Message-ID: <20231018075038.2740534-1-s-vadapalli@ti.com> (raw)

The ks_pcie_v3_65_add_bus() member of "ks_pcie_ops" was added for
platforms using DW PCIe IP-core version 3.65a. The AM654x SoC uses
DW PCIe IP-core version 4.90a and ks_pcie_v3_65_add_bus() is not
applicable to it.

The commit which added support for the AM654x SoC has reused majority
of the functions with the help of the "is_am6" flag to handle AM654x
separately where applicable. Thus, make use of the "is_am6" flag and
change ks_pcie_v3_65_add_bus() to no-op for AM654x SoC.

Fixes: 18b0415bc802 ("PCI: keystone: Add support for PCIe RC in AM654x Platforms")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,

This patch is based on linux-next tagged next-20231018.

The v1 of this patch is at:
https://lore.kernel.org/r/20231011123451.34827-1-s-vadapalli@ti.com/

While there are a lot of changes since v1 and this patch could have been
posted as a v1 patch itself, I decided to post it as the v2 of the patch
mentioned above since it aims to address the issue described by the v1
patch and is similar in that sense. However, the solution to the issue
described in the v1 patch appears to be completely different from what
was implemented in the v1 patch. Thus, the commit message and subject of
this patch have been modified accordingly.

Changes since v1:
- Updated patch subject and commit message.
- Determined that issue is not with the absence of Link as mentioned in
  v1 patch. Even with Link up and endpoint device connected, if
  ks_pcie_v3_65_add_bus() is invoked and executed, all reads to the
  MSI-X offsets return 0xffffffff when pcieport driver attempts to setup
  AER and PME services. The all Fs return value indicates that the MSI-X
  configuration is failing even if Endpoint device is connected. This is
  because the ks_pcie_v3_65_add_bus() function is not applicable to the
  AM654x SoC which uses DW PCIe IP-core version 4.90a.

Regards,
Siddharth.

 drivers/pci/controller/dwc/pci-keystone.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 0def919f89fa..3abd59335574 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -459,7 +459,7 @@ static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 
-	if (!pci_is_root_bus(bus))
+	if (!pci_is_root_bus(bus) || ks_pcie->is_am6)
 		return 0;
 
 	/* Configure and set up BAR0 */
-- 
2.34.1


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