* [RESEND PATCH v2] arm64: dts: Update cache properties for socionext
@ 2023-10-20 19:50 Rob Herring
2023-10-20 21:26 ` Krzysztof Kozlowski
2023-10-20 21:45 ` Krzysztof Kozlowski
0 siblings, 2 replies; 4+ messages in thread
From: Rob Herring @ 2023-10-20 19:50 UTC (permalink / raw)
To: soc, Krzysztof Kozlowski, Conor Dooley, Kunihiko Hayashi,
Masami Hiramatsu
Cc: Pierre Gondois, devicetree, linux-arm-kernel, linux-kernel
From: Pierre Gondois <pierre.gondois@arm.com>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com
Signed-off-by: Rob Herring <robh@kernel.org>
---
I noticed this one fell thru the cracks from the rest of the series.
Arnd, Can you take this directly.
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 7bb36b071475..54e58d945fd7 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -52,6 +52,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 4e2171630272..18390cba2eda 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -86,10 +86,12 @@ cpu3: cpu@101 {
a72_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 38ccfb46ea42..56e037900818 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -83,6 +83,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.42.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [RESEND PATCH v2] arm64: dts: Update cache properties for socionext
2023-10-20 19:50 [RESEND PATCH v2] arm64: dts: Update cache properties for socionext Rob Herring
@ 2023-10-20 21:26 ` Krzysztof Kozlowski
2023-10-23 1:53 ` Kunihiko Hayashi
2023-10-20 21:45 ` Krzysztof Kozlowski
1 sibling, 1 reply; 4+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-20 21:26 UTC (permalink / raw)
To: Rob Herring, soc, Krzysztof Kozlowski, Conor Dooley,
Kunihiko Hayashi, Masami Hiramatsu
Cc: Pierre Gondois, devicetree, linux-arm-kernel, linux-kernel
On 20/10/2023 21:50, Rob Herring wrote:
> From: Pierre Gondois <pierre.gondois@arm.com>
>
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> I noticed this one fell thru the cracks from the rest of the series.
>
> Arnd, Can you take this directly.
A bit after Pierre - in April 2023 - I sent similar which was said to be
"applied":
https://lore.kernel.org/all/f9a2c0d7-a78d-9368-f9bb-e8aba11e7d81@socionext.com/
Maybe the Socionext status in MAINTAINERS should be odd fixes?
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [RESEND PATCH v2] arm64: dts: Update cache properties for socionext
2023-10-20 21:26 ` Krzysztof Kozlowski
@ 2023-10-23 1:53 ` Kunihiko Hayashi
0 siblings, 0 replies; 4+ messages in thread
From: Kunihiko Hayashi @ 2023-10-23 1:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, soc, Krzysztof Kozlowski,
Conor Dooley, Masami Hiramatsu
Cc: Pierre Gondois, devicetree, linux-arm-kernel, linux-kernel
Hi Krzysztof, Rob,
On 2023/10/21 6:26, Krzysztof Kozlowski wrote:
> On 20/10/2023 21:50, Rob Herring wrote:
>> From: Pierre Gondois <pierre.gondois@arm.com>
>>
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>> Link:
>> https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com
>> Signed-off-by: Rob Herring <robh@kernel.org>
>> ---
>> I noticed this one fell thru the cracks from the rest of the series.
>>
>> Arnd, Can you take this directly.
>
> A bit after Pierre - in April 2023 - I sent similar which was said to be
> "applied":
> https://lore.kernel.org/all/f9a2c0d7-a78d-9368-f9bb-e8aba11e7d81@socionext.com/
>
> Maybe the Socionext status in MAINTAINERS should be odd fixes?
Sorry my mistake.
I thought Pierre's patch had been already applied, however,
I set Krzysztof's patch to "applied" but it was missing from the post to soc.
Since Krzysztof's patch includes the same "cache-level" lines as Pierre's,
the lines needs to be removed.
I'll post the update series including both to soc.
Thank you,
---
Best Regards
Kunihiko Hayashi
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RESEND PATCH v2] arm64: dts: Update cache properties for socionext
2023-10-20 19:50 [RESEND PATCH v2] arm64: dts: Update cache properties for socionext Rob Herring
2023-10-20 21:26 ` Krzysztof Kozlowski
@ 2023-10-20 21:45 ` Krzysztof Kozlowski
1 sibling, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-20 21:45 UTC (permalink / raw)
To: Rob Herring, soc, Krzysztof Kozlowski, Conor Dooley,
Kunihiko Hayashi, Masami Hiramatsu
Cc: Pierre Gondois, devicetree, linux-arm-kernel, linux-kernel
On 20/10/2023 21:50, Rob Herring wrote:
> From: Pierre Gondois <pierre.gondois@arm.com>
>
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-10-20 21:26 ` Krzysztof Kozlowski
2023-10-23 1:53 ` Kunihiko Hayashi
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