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From: Conor Dooley <conor@kernel.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: acme@kernel.org, adrian.hunter@intel.com,
	ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
	andre.przywara@arm.com, anup@brainfault.org,
	aou@eecs.berkeley.edu, atishp@atishpatra.org,
	conor+dt@kernel.org, conor.dooley@microchip.com,
	devicetree@vger.kernel.org, dminus@andestech.com,
	evan@rivosinc.com, geert+renesas@glider.be, guoren@kernel.org,
	heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com,
	jolsa@kernel.org, jszhang@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
	locus84@andestech.com, magnus.damm@gmail.com,
	mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
	namhyung@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, peterz@infradead.org,
	prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org,
	robh+dt@kernel.org, samuel@sholland.org,
	sunilvl@ventanamicro.com, tglx@linutronix.de,
	tim609@andestech.com, uwu@icenowy.me, wens@csie.org,
	will@kernel.org, ycliang@andestech.com
Subject: Re: [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string
Date: Mon, 23 Oct 2023 14:15:21 +0100	[thread overview]
Message-ID: <20231023-contented-passcode-2e8d082afed4@spud> (raw)
In-Reply-To: <20231023004100.2663486-5-peterlin@andestech.com>


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On Mon, Oct 23, 2023 at 08:40:51AM +0800, Yu Chien Peter Lin wrote:
> Add "andestech,cpu-intc" compatible string which indicates that
> Andes specific local interrupt is supported on the core,
> e.g. AX45MP cores have 3 types of non-standard local interrupt
> can be handled in supervisor mode:
> 
> - Slave port ECC error interrupt
> - Bus write transaction error interrupt
> - Performance monitor overflow interrupt
> 
> These interrupts are enabled/disabled via a custom register
> SLIE instead of the standard interrupt enable register SIE.
> 
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - Updated commit message
>   - Fixed possible compatibles for Andes INTC
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..4c1bbcf07406 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -99,7 +99,12 @@ properties:
>          const: 1
>  
>        compatible:
> -        const: riscv,cpu-intc
> +        oneOf:
> +          - items:
> +              - enum:
> +                  - andestech,cpu-intc

Why is this an enum rather than const? What other entries are we going
to add here in the near future?

> +              - const: riscv,cpu-intc

My follow-up question, if my original question on the v2 series had been
answered was going to be about how generic the "andestech,cpu-intc"
compatible is.

Having a cpu-specific compatible in addition to "andestech,cpu-intc"
one makes sense to me, so that we can differentiate between
implementations/integrations of this intc, especially if Andes have no
plans to move to the standard implementation.

Cheers,
Conor.

> +          - const: riscv,cpu-intc
>  
>        interrupt-controller: true
>  
> -- 
> 2.34.1
> 

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  reply	other threads:[~2023-10-23 13:16 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23  0:40 [PATCH v3 RESEND 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-23  0:40 ` [PATCH v3 RESEND 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-23  9:23   ` Conor Dooley
2023-10-23  0:40 ` [RFC PATCH v3 RESEND 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Yu Chien Peter Lin
2023-10-27  7:12   ` Thomas Gleixner
2023-10-30  7:12     ` Yu-Chien Peter Lin
2023-10-23  0:40 ` [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-27  7:13   ` Thomas Gleixner
2023-10-23  0:40 ` [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-23 13:15   ` Conor Dooley [this message]
2023-10-26  8:50     ` Yu-Chien Peter Lin
2023-10-23  0:40 ` [PATCH v3 RESEND 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-23  0:40 ` [PATCH v3 RESEND 06/13] perf: RISC-V: Eliminate redundant IRQ enable/disable operations Yu Chien Peter Lin
2023-10-23  0:40 ` [RFC PATCH v3 RESEND 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-10-23 11:56   ` Conor Dooley
2023-10-23  0:40 ` [PATCH v3 RESEND 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-10-23  0:40 ` [RFC PATCH v3 RESEND 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-10-23 12:25   ` Conor Dooley
2023-10-23  0:40 ` [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-10-23 12:03   ` Conor Dooley
2023-10-26  8:22     ` Yu-Chien Peter Lin
2023-10-26 14:09       ` Conor Dooley
2023-10-27  7:22         ` Yu-Chien Peter Lin
2023-10-23  0:40 ` [RFC PATCH v3 RESEND 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-10-23  0:40 ` [PATCH v3 RESEND 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-10-23  0:41 ` [PATCH v3 RESEND 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin

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