From: Conor Dooley <conor@kernel.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
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Subject: Re: [PATCH v3 RESEND 01/13] riscv: errata: Rename defines for Andes
Date: Mon, 23 Oct 2023 10:23:10 +0100 [thread overview]
Message-ID: <20231023-splashing-dandy-1effebb9ec30@spud> (raw)
In-Reply-To: <20231023004100.2663486-2-peterlin@andestech.com>
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On Mon, Oct 23, 2023 at 08:40:48AM +0800, Yu Chien Peter Lin wrote:
> Using "ANDES" rather than "ANDESTECH" to unify the naming
> convention with directory, file names, Kconfig options
> and other definitions.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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next prev parent reply other threads:[~2023-10-23 9:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 0:40 [PATCH v3 RESEND 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-23 9:23 ` Conor Dooley [this message]
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Yu Chien Peter Lin
2023-10-27 7:12 ` Thomas Gleixner
2023-10-30 7:12 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-27 7:13 ` Thomas Gleixner
2023-10-23 0:40 ` [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-23 13:15 ` Conor Dooley
2023-10-26 8:50 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 06/13] perf: RISC-V: Eliminate redundant IRQ enable/disable operations Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-10-23 11:56 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-10-23 12:25 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-10-23 12:03 ` Conor Dooley
2023-10-26 8:22 ` Yu-Chien Peter Lin
2023-10-26 14:09 ` Conor Dooley
2023-10-27 7:22 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-10-23 0:41 ` [PATCH v3 RESEND 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
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