From: Ben Wolsieffer <ben.wolsieffer@hefring.com>
To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Alain Volmat <alain.volmat@foss.st.com>,
Erwan Leray <erwan.leray@foss.st.com>,
Fabrice Gasnier <fabrice.gasnier@foss.st.com>,
Ben Wolsieffer <ben.wolsieffer@hefring.com>
Subject: [PATCH 5/5] ARM: dts: stm32: add SPI support on STM32F746
Date: Wed, 1 Nov 2023 11:08:10 -0400 [thread overview]
Message-ID: <20231101150811.2747455-6-ben.wolsieffer@hefring.com> (raw)
In-Reply-To: <20231101150811.2747455-1-ben.wolsieffer@hefring.com>
Add device tree nodes for the STM32F746 SPI controllers.
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
---
arch/arm/boot/dts/st/stm32f746.dtsi | 60 +++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
index cce6ab0e4617..15ad965f8d96 100644
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ b/arch/arm/boot/dts/st/stm32f746.dtsi
@@ -281,6 +281,26 @@ gcan3: gcan@40003600 {
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
+ spi2: spi@40003800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
+ status = "disabled";
+ };
+
+ spi3: spi@40003c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40003c00 0x400>;
+ interrupts = <51>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@@ -498,6 +518,26 @@ sdio1: mmc@40012c00 {
status = "disabled";
};
+ spi1: spi@40013000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40013000 0x400>;
+ interrupts = <35>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
+ status = "disabled";
+ };
+
+ spi4: spi@40013400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40013400 0x400>;
+ interrupts = <84>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
+ status = "disabled";
+ };
+
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
@@ -562,6 +602,26 @@ pwm {
};
};
+ spi5: spi@40015000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40015000 0x400>;
+ interrupts = <85>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
+ status = "disabled";
+ };
+
+ spi6: spi@40015400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40015400 0x400>;
+ interrupts = <86>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
+ status = "disabled";
+ };
+
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
--
2.42.0
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prev parent reply other threads:[~2023-11-01 15:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-01 15:08 [PATCH 0/5] Add STM32F7 SPI support Ben Wolsieffer
2023-11-01 15:08 ` [PATCH 1/5] spi: stm32: rename stm32f4_* to stm32fx_* Ben Wolsieffer
2023-11-01 15:08 ` [PATCH 2/5] spi: stm32: use callbacks for read_rx and write_tx Ben Wolsieffer
2023-11-01 15:08 ` [PATCH 3/5] dt-bindings: spi: add stm32f7-spi compatible Ben Wolsieffer
2023-11-01 15:45 ` Conor Dooley
2023-11-01 15:08 ` [PATCH 4/5] spi: stm32: add STM32F7 support Ben Wolsieffer
2023-11-01 15:08 ` Ben Wolsieffer [this message]
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