From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33BC7C4167B for ; Mon, 6 Nov 2023 23:16:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vmI3d1Sx+Dqr0/zpdHIZz+TIlHUZdLXyk0pCt2Iz/hs=; b=i1I7zcZlxLMr32 NAa9LbIG8CAYTHQ6NA8Yt0clBjRjMhTUGrGYpP3L6GqtVO+qqLvbxOdhr/m7mUFK8ImGZub+Kb6n0 epyIIPdtd6Zf0xNf+t7204oMmhM/8f+9PUaLVmEuXOGzwhY9lIT16oL5QkXuzpxQzk8UG68Gf3ajj R1AUtTiIoFuTPcTbN1rwFG4Gj0N8/Qztn7oZFC+l9+rHChjSywHW9PRFr1lQFCBbvMIfqssrxHZEZ OGpAKFVUKGvnm4qwD284LPHol412onca/WRxjBpega486VJRfNBOvYtw2v6P3MJt5CDPSYo8tcT9f PlQ8W1zOTSk9OSOuCQKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r08pI-0007fN-17; Mon, 06 Nov 2023 23:16:12 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r08pD-0007dV-1Y for linux-arm-kernel@lists.infradead.org; Mon, 06 Nov 2023 23:16:09 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 005CE61053; Mon, 6 Nov 2023 23:16:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5AB2C433CC; Mon, 6 Nov 2023 23:16:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699312566; bh=2VpchQM44d7HzgCX3wgizYzX0JgaRvK/XXJiO68xAFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PmCTfUnl8VPRuAhiuCGEx3vC6+9R54Bl1IYJVAOffYjX72Wf3qaMJGCi50r5DIAQz 7TL1gh4EDbe0322aaXa6b9xpR1OPbAd1Gn4NQ6gYbSZe58TnK6NbxZjkFv7z2sYR44 FXe+JCYbUBCP8vVYoZEmVwBJMkVk1vzV4Vo5Ou9xQcwujIRLhodZUr4q74yn2oMA8H 5M+X/XCCewXaWhJO006EGroNQHrWsY20/2eqB4TMyOR1+j2vzDyj+f86SlVF7iXRyC HkYAqj+bRX4tkPiasIC5hBfuQMV5Mf1dJJ9ewp2/4Cylzc3RnPAZ0u8/vHUXQVoa47 jo6JIzlaldvSw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 6.1 07/11] clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware Date: Mon, 6 Nov 2023 18:15:41 -0500 Message-ID: <20231106231553.3735366-7-sashal@kernel.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231106231553.3735366-1-sashal@kernel.org> References: <20231106231553.3735366-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.61 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231106_151607_604959_EB9D4C2C X-CRM114-Status: GOOD ( 17.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Alexandre Belloni , Daniel Lezcano , claudiu.beznea@tuxon.dev, tglx@linutronix.de, Ronald Wahl , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ronald Wahl [ Upstream commit 6d3bc4c02d59996d1d3180d8ed409a9d7d5900e0 ] On SAM9 hardware two cascaded 16 bit timers are used to form a 32 bit high resolution timer that is used as scheduler clock when the kernel has been configured that way (CONFIG_ATMEL_CLOCKSOURCE_TCB). The driver initially triggers a reset-to-zero of the two timers but this reset is only performed on the next rising clock. For the first timer this is ok - it will be in the next 60ns (16MHz clock). For the chained second timer this will only happen after the first timer overflows, i.e. after 2^16 clocks (~4ms with a 16MHz clock). So with other words the scheduler clock resets to 0 after the first 2^16 clock cycles. It looks like that the scheduler does not like this and behaves wrongly over its lifetime, e.g. some tasks are scheduled with a long delay. Why that is and if there are additional requirements for this behaviour has not been further analysed. There is a simple fix for resetting the second timer as well when the first timer is reset and this is to set the ATMEL_TC_ASWTRG_SET bit in the Channel Mode register (CMR) of the first timer. This will also rise the TIOA line (clock input of the second timer) when a software trigger respective SYNC is issued. Signed-off-by: Ronald Wahl Acked-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20231007161803.31342-1-rwahl@gmx.de Signed-off-by: Sasha Levin --- drivers/clocksource/timer-atmel-tcb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c index 27af17c995900..2a90c92a9182a 100644 --- a/drivers/clocksource/timer-atmel-tcb.c +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -315,6 +315,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP /* free-run */ + | ATMEL_TC_ASWTRG_SET /* TIOA0 rises at software trigger */ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ tcaddr + ATMEL_TC_REG(0, CMR)); -- 2.42.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel