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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH 07/12] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is non-zero
Date: Mon, 13 Nov 2023 17:42:39 +0000	[thread overview]
Message-ID: <20231113174244.3026520-8-maz@kernel.org> (raw)
In-Reply-To: <20231113174244.3026520-1-maz@kernel.org>

For CPUs that have ID_AA64MMFR4_EL1.E2H0 as non-zero, it is important
to avoid the boot path that sets HCR_EL2.E2H=0. Fortunately, we
already have this path to cope with fruity CPUs.

Tweak init_el2 to look at ID_AA64MMFR4_EL1.E2H0 first.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kernel/head.S | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7b236994f0e1..5853540f7809 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -584,25 +584,34 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
 	mov_q	x1, INIT_SCTLR_EL1_MMU_OFF
 
 	/*
-	 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
-	 * making it impossible to start in nVHE mode. Is that
-	 * compliant with the architecture? Absolutely not!
+	 * Compliant CPUs advertise their VHE-onlyness with
+	 * ID_AA64MMFR4_EL1.E2H0=0b111x. HCR_EL2.E2H can be
+	 * RES1 in that case.
+	 *
+	 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, but
+	 * don't advertise it (they predate this relaxation).
 	 */
+	mrs_s	x0, SYS_ID_AA64MMFR4_EL1
+	ubfx	x0, x0, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
+	and	x0, x0, #0b1110
+	cmp	x0, #0b1110
+	b.eq	1f
+
 	mrs	x0, hcr_el2
 	and	x0, x0, #HCR_E2H
-	cbz	x0, 1f
-
+	cbz	x0, 2f
+1:
 	/* Set a sane SCTLR_EL1, the VHE way */
 	pre_disable_mmu_workaround
 	msr_s	SYS_SCTLR_EL12, x1
 	mov	x2, #BOOT_CPU_FLAG_E2H
-	b	2f
+	b	3f
 
-1:
+2:
 	pre_disable_mmu_workaround
 	msr	sctlr_el1, x1
 	mov	x2, xzr
-2:
+3:
 	__init_el2_nvhe_prepare_eret
 
 	mov	w0, #BOOT_CPU_MODE_EL2
-- 
2.39.2


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  parent reply	other threads:[~2023-11-13 17:44 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-13 17:42 [PATCH 00/12] arm64: Add support for FEAT_E2H0, or lack thereof Marc Zyngier
2023-11-13 17:42 ` [PATCH 01/12] arm64: cpufeatures: Correctly handle signed values Marc Zyngier
2023-11-17  0:45   ` Oliver Upton
2023-11-13 17:42 ` [PATCH 02/12] arm64: cpufeature: Correctly display signed override values Marc Zyngier
2023-11-17  0:46   ` Oliver Upton
2023-11-13 17:42 ` [PATCH 03/12] arm64: sysreg: Add layout for ID_AA64MMFR4_EL1 Marc Zyngier
2023-11-13 17:42 ` [PATCH 04/12] arm64: cpufeature: Add ID_AA64MMFR4_EL1 handling Marc Zyngier
2023-11-17  0:48   ` Oliver Upton
2023-11-13 17:42 ` [PATCH 05/12] arm64: cpufeature: Detect E2H0 not being implemented Marc Zyngier
2023-11-17  0:56   ` Oliver Upton
2023-11-17 12:21     ` Marc Zyngier
2023-11-13 17:42 ` [PATCH 06/12] arm64: cpufeature: Detect HCR_EL2.NV1 being RES0 Marc Zyngier
2023-11-13 17:42 ` Marc Zyngier [this message]
2023-11-17  0:23   ` [PATCH 07/12] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is non-zero Oliver Upton
2023-11-17 12:17     ` Marc Zyngier
2023-11-17 18:01       ` Oliver Upton
2023-11-13 17:42 ` [PATCH 08/12] arm64: Add override for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-13 17:42 ` [PATCH 09/12] arm64: Add MIDR-based override infrastructure Marc Zyngier
2023-11-13 17:42 ` [PATCH 10/12] arm64: Add MIDR-based overrides for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-13 17:42 ` [PATCH 11/12] KVM: arm64: Expose ID_AA64MMFR4_EL1 to guests Marc Zyngier
2023-11-13 17:42 ` [PATCH 12/12] KVM: arm64: Force guest's HCR_EL2.E2H RES1 when NV1 is not implemented Marc Zyngier

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