From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
To: linux-media@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com
Cc: Hugues Fruchet <hugues.fruchet@foss.st.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andrzej Pietrasiewicz <andrzej.p@collabora.com>,
Benjamin Gaignard <benjamin.gaignard@collabora.com>,
Daniel Almeida <daniel.almeida@collabora.com>,
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Nicolas Dufresne <nicolas.dufresne@collabora.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
kernel@collabora.com
Subject: [RFC 4/6] media: verisilicon: Update H1 register definitions
Date: Thu, 16 Nov 2023 16:48:14 +0100 [thread overview]
Message-ID: <20231116154816.70959-5-andrzej.p@collabora.com> (raw)
In-Reply-To: <20231116154816.70959-1-andrzej.p@collabora.com>
Add definition of register at offset 0x00c.
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
---
drivers/media/platform/verisilicon/hantro_h1_regs.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/media/platform/verisilicon/hantro_h1_regs.h b/drivers/media/platform/verisilicon/hantro_h1_regs.h
index c1c66c934a24..efb46da23eab 100644
--- a/drivers/media/platform/verisilicon/hantro_h1_regs.h
+++ b/drivers/media/platform/verisilicon/hantro_h1_regs.h
@@ -23,6 +23,15 @@
#define H1_REG_AXI_CTRL_INPUT_SWAP32 BIT(2)
#define H1_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1)
#define H1_REG_AXI_CTRL_INPUT_SWAP8 BIT(0)
+#define H1_REG_DEVICE_CTRL 0x00c
+#define H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP8 BIT(27)
+#define H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP16 BIT(26)
+#define H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP32 BIT(25)
+#define H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP8 BIT(24)
+#define H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP16 BIT(23)
+#define H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP32 BIT(22)
+#define H1_REG_DEVICE_CTRL_INPUT_READ_1MB BIT(21)
+#define H1_REG_DEVICE_CTRL_AXI_DUAL_CHANNEL BIT(20)
#define H1_REG_ADDR_OUTPUT_STREAM 0x014
#define H1_REG_ADDR_OUTPUT_CTRL 0x018
#define H1_REG_ADDR_REF_LUMA 0x01c
--
2.25.1
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next prev parent reply other threads:[~2023-11-16 15:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-16 15:48 [RFC 0/6] H.264 stateless encoder RFC 0/6 Andrzej Pietrasiewicz
2023-11-16 15:48 ` [RFC 1/6] media: verisilicon Correct a typo in H1_REG_ENC_CTRL2_DEBLOCKING_FILTER_MODE Andrzej Pietrasiewicz
2023-11-16 15:50 ` Chen-Yu Tsai
2023-11-16 15:48 ` [RFC 2/6] media: verisilicon: Correct a typo in H1_REG_MAD_CTRL_MAD_THRESHOLD Andrzej Pietrasiewicz
2023-11-16 15:50 ` Chen-Yu Tsai
2023-11-16 15:48 ` [RFC 3/6] media: verisilicon: Improve constant's name Andrzej Pietrasiewicz
2023-11-17 6:11 ` Chen-Yu Tsai
2023-11-17 8:44 ` Andrzej Pietrasiewicz
2023-11-16 15:48 ` Andrzej Pietrasiewicz [this message]
2023-11-17 6:56 ` [RFC 4/6] media: verisilicon: Update H1 register definitions Chen-Yu Tsai
2023-11-17 8:46 ` Andrzej Pietrasiewicz
2023-11-16 15:48 ` [RFC 5/6] media: uapi: Add H.264 stateless encoding uAPI Andrzej Pietrasiewicz
2023-11-16 15:48 ` [RFC 6/6] media: verisilicon: Add H.264 stateless encoder Andrzej Pietrasiewicz
2023-11-18 23:19 ` [RFC 0/6] H.264 stateless encoder RFC 0/6 Adam Ford
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