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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Jintack Lim <jintack@cs.columbia.edu>,
	Russell King <rmk+kernel@armlinux.org.uk>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v11 10/43] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg()
Date: Mon, 20 Nov 2023 13:09:54 +0000	[thread overview]
Message-ID: <20231120131027.854038-11-maz@kernel.org> (raw)
In-Reply-To: <20231120131027.854038-1-maz@kernel.org>

KVM internally uses accessor functions when reading or writing the
guest's system registers. This takes care of accessing either the stored
copy or using the "live" EL1 system registers when the host uses VHE.

With the introduction of virtual EL2 we add a bunch of EL2 system
registers, which now must also be taken care of:

- If the guest is running in vEL2, and we access an EL1 sysreg, we must
  revert to the stored version of that, and not use the CPU's copy.

- If the guest is running in vEL1, and we access an EL2 sysreg, we must
  also use the stored version, since the CPU carries the EL1 copy.

- Some EL2 system registers are supposed to affect the current execution
  of the system, so we need to put them into their respective EL1
  counterparts. For this we need to define a mapping between the two.

- Some EL2 system registers have a different format than their EL1
  counterpart, so we need to translate them before writing them to the
  CPU. This is done using an (optional) translate function in the map.

All of these cases are now wrapped into the existing accessor functions,
so KVM users wouldn't need to care whether they access EL2 or EL1
registers and also which state the guest is in.

Reviewed-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Co-developed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h |   2 +
 arch/arm64/kvm/sys_regs.c         | 129 ++++++++++++++++++++++++++++--
 2 files changed, 126 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 9e8cd2bb95c3..f17fb7c42973 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -907,6 +907,7 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
 	case AMAIR_EL1:		*val = read_sysreg_s(SYS_AMAIR_EL12);	break;
 	case CNTKCTL_EL1:	*val = read_sysreg_s(SYS_CNTKCTL_EL12);	break;
 	case ELR_EL1:		*val = read_sysreg_s(SYS_ELR_EL12);	break;
+	case SPSR_EL1:		*val = read_sysreg_s(SYS_SPSR_EL12);	break;
 	case PAR_EL1:		*val = read_sysreg_par();		break;
 	case DACR32_EL2:	*val = read_sysreg_s(SYS_DACR32_EL2);	break;
 	case IFSR32_EL2:	*val = read_sysreg_s(SYS_IFSR32_EL2);	break;
@@ -951,6 +952,7 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
 	case AMAIR_EL1:		write_sysreg_s(val, SYS_AMAIR_EL12);	break;
 	case CNTKCTL_EL1:	write_sysreg_s(val, SYS_CNTKCTL_EL12);	break;
 	case ELR_EL1:		write_sysreg_s(val, SYS_ELR_EL12);	break;
+	case SPSR_EL1:		write_sysreg_s(val, SYS_SPSR_EL12);	break;
 	case PAR_EL1:		write_sysreg_s(val, SYS_PAR_EL1);	break;
 	case DACR32_EL2:	write_sysreg_s(val, SYS_DACR32_EL2);	break;
 	case IFSR32_EL2:	write_sysreg_s(val, SYS_IFSR32_EL2);	break;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c31fddc1591d..92bb91e520a8 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -72,24 +72,143 @@ static bool write_to_read_only(struct kvm_vcpu *vcpu,
 			"sys_reg write to read-only register");
 }
 
+#define PURE_EL2_SYSREG(el2)						\
+	case el2: {							\
+		*el1r = el2;						\
+		return true;						\
+	}
+
+#define MAPPED_EL2_SYSREG(el2, el1, fn)					\
+	case el2: {							\
+		*xlate = fn;						\
+		*el1r = el1;						\
+		return true;						\
+	}
+
+static bool get_el2_to_el1_mapping(unsigned int reg,
+				   unsigned int *el1r, u64 (**xlate)(u64))
+{
+	switch (reg) {
+		PURE_EL2_SYSREG(  VPIDR_EL2	);
+		PURE_EL2_SYSREG(  VMPIDR_EL2	);
+		PURE_EL2_SYSREG(  ACTLR_EL2	);
+		PURE_EL2_SYSREG(  HCR_EL2	);
+		PURE_EL2_SYSREG(  MDCR_EL2	);
+		PURE_EL2_SYSREG(  HSTR_EL2	);
+		PURE_EL2_SYSREG(  HACR_EL2	);
+		PURE_EL2_SYSREG(  VTTBR_EL2	);
+		PURE_EL2_SYSREG(  VTCR_EL2	);
+		PURE_EL2_SYSREG(  RVBAR_EL2	);
+		PURE_EL2_SYSREG(  TPIDR_EL2	);
+		PURE_EL2_SYSREG(  HPFAR_EL2	);
+		PURE_EL2_SYSREG(  CNTHCTL_EL2	);
+		MAPPED_EL2_SYSREG(SCTLR_EL2,   SCTLR_EL1,
+				  translate_sctlr_el2_to_sctlr_el1	     );
+		MAPPED_EL2_SYSREG(CPTR_EL2,    CPACR_EL1,
+				  translate_cptr_el2_to_cpacr_el1	     );
+		MAPPED_EL2_SYSREG(TTBR0_EL2,   TTBR0_EL1,
+				  translate_ttbr0_el2_to_ttbr0_el1	     );
+		MAPPED_EL2_SYSREG(TTBR1_EL2,   TTBR1_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(TCR_EL2,     TCR_EL1,
+				  translate_tcr_el2_to_tcr_el1		     );
+		MAPPED_EL2_SYSREG(VBAR_EL2,    VBAR_EL1,    NULL	     );
+		MAPPED_EL2_SYSREG(AFSR0_EL2,   AFSR0_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(AFSR1_EL2,   AFSR1_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(ESR_EL2,     ESR_EL1,     NULL	     );
+		MAPPED_EL2_SYSREG(FAR_EL2,     FAR_EL1,     NULL	     );
+		MAPPED_EL2_SYSREG(MAIR_EL2,    MAIR_EL1,    NULL	     );
+		MAPPED_EL2_SYSREG(AMAIR_EL2,   AMAIR_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(ELR_EL2,     ELR_EL1,	    NULL	     );
+		MAPPED_EL2_SYSREG(SPSR_EL2,    SPSR_EL1,    NULL	     );
+	default:
+		return false;
+	}
+}
+
 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
 {
 	u64 val = 0x8badf00d8badf00d;
+	u64 (*xlate)(u64) = NULL;
+	unsigned int el1r;
+
+	if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
+		goto memory_read;
 
-	if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
-	    __vcpu_read_sys_reg_from_cpu(reg, &val))
+	if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
+		if (!is_hyp_ctxt(vcpu))
+			goto memory_read;
+
+		/*
+		 * If this register does not have an EL1 counterpart,
+		 * then read the stored EL2 version.
+		 */
+		if (reg == el1r)
+			goto memory_read;
+
+		/*
+		 * If we have a non-VHE guest and that the sysreg
+		 * requires translation to be used at EL1, use the
+		 * in-memory copy instead.
+		 */
+		if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
+			goto memory_read;
+
+		/* Get the current version of the EL1 counterpart. */
+		WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
+		return val;
+	}
+
+	/* EL1 register can't be on the CPU if the guest is in vEL2. */
+	if (unlikely(is_hyp_ctxt(vcpu)))
+		goto memory_read;
+
+	if (__vcpu_read_sys_reg_from_cpu(reg, &val))
 		return val;
 
+memory_read:
 	return __vcpu_sys_reg(vcpu, reg);
 }
 
 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 {
-	if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
-	    __vcpu_write_sys_reg_to_cpu(val, reg))
+	u64 (*xlate)(u64) = NULL;
+	unsigned int el1r;
+
+	if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
+		goto memory_write;
+
+	if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
+		if (!is_hyp_ctxt(vcpu))
+			goto memory_write;
+
+		/*
+		 * Always store a copy of the write to memory to avoid having
+		 * to reverse-translate virtual EL2 system registers for a
+		 * non-VHE guest hypervisor.
+		 */
+		__vcpu_sys_reg(vcpu, reg) = val;
+
+		/* No EL1 counterpart? We're done here.? */
+		if (reg == el1r)
+			return;
+
+		if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
+			val = xlate(val);
+
+		/* Redirect this to the EL1 version of the register. */
+		WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
+		return;
+	}
+
+	/* EL1 register can't be on the CPU if the guest is in vEL2. */
+	if (unlikely(is_hyp_ctxt(vcpu)))
+		goto memory_write;
+
+	if (__vcpu_write_sys_reg_to_cpu(val, reg))
 		return;
 
-	__vcpu_sys_reg(vcpu, reg) = val;
+memory_write:
+	 __vcpu_sys_reg(vcpu, reg) = val;
 }
 
 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
-- 
2.39.2


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  parent reply	other threads:[~2023-11-20 14:15 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-20 13:09 [PATCH v11 00/43] KVM: arm64: Nested Virtualization support (FEAT_NV2 only) Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 01/43] arm64: cpufeatures: Restrict NV support to FEAT_NV2 Marc Zyngier
2023-11-21  9:07   ` Ganapatrao Kulkarni
2023-11-21  9:27     ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 02/43] KVM: arm64: nv: Hoist vcpu_has_nv() into is_hyp_ctxt() Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 03/43] KVM: arm64: nv: Compute NV view of idregs as a one-off Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 04/43] KVM: arm64: nv: Drop EL12 register traps that are redirected to VNCR Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 05/43] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 06/43] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 07/43] KVM: arm64: Introduce a bad_trap() primitive for unexpected trap handling Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 08/43] KVM: arm64: nv: Add EL2_REG_VNCR()/EL2_REG_REDIR() sysreg helpers Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 09/43] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier
2023-11-20 13:09 ` Marc Zyngier [this message]
2023-11-20 13:09 ` [PATCH v11 11/43] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 12/43] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 13/43] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 14/43] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 15/43] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 16/43] KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2 Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 17/43] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier
2024-01-23  9:55   ` Ganapatrao Kulkarni
2024-01-23 14:26     ` Marc Zyngier
2024-01-25  8:14       ` Ganapatrao Kulkarni
2024-01-25  8:58         ` Marc Zyngier
2024-01-31  9:39           ` Ganapatrao Kulkarni
2024-01-31 13:50             ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 18/43] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 19/43] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2024-01-17 14:53   ` Joey Gouly
2024-01-17 15:53     ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 20/43] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 21/43] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 22/43] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 23/43] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 24/43] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 25/43] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 26/43] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 27/43] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 28/43] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 29/43] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 30/43] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 31/43] KVM: arm64: nv: Don't block in WFI from nested state Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 32/43] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 33/43] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 34/43] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 35/43] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 36/43] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 37/43] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 38/43] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 39/43] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 40/43] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 41/43] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 42/43] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 43/43] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2023-11-21  8:51 ` [PATCH v11 00/43] KVM: arm64: Nested Virtualization support (FEAT_NV2 only) Ganapatrao Kulkarni
2023-11-21  9:08   ` Marc Zyngier
2023-11-21  9:26     ` Ganapatrao Kulkarni
2023-11-21  9:41       ` Marc Zyngier
2023-11-22 11:10         ` Ganapatrao Kulkarni
2023-11-22 11:39           ` Marc Zyngier
2023-11-21 16:49 ` Miguel Luis
2023-11-21 19:02   ` Marc Zyngier
2023-11-23 16:21     ` Miguel Luis
2023-11-23 16:44       ` Marc Zyngier
2023-11-24  9:50         ` Ganapatrao Kulkarni
2023-11-24 10:19           ` Marc Zyngier
2023-11-24 12:34             ` Ganapatrao Kulkarni
2023-11-24 12:51               ` Marc Zyngier
2023-11-24 13:22                 ` Ganapatrao Kulkarni
2023-11-24 14:32                   ` Marc Zyngier
2023-11-27  7:26                     ` Ganapatrao Kulkarni
2023-11-27  9:22                       ` Marc Zyngier
2023-11-27 10:59                         ` Ganapatrao Kulkarni
2023-11-27 11:45                           ` Marc Zyngier
2023-11-27 12:18                             ` Ganapatrao Kulkarni
2023-11-27 13:57                               ` Marc Zyngier
2023-12-18 12:39 ` Marc Zyngier
2023-12-18 19:51   ` Oliver Upton
2023-12-19 10:32 ` (subset) " Marc Zyngier

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