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d="asc'?scan'208";a="12937545" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Nov 2023 07:39:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 23 Nov 2023 07:39:06 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Thu, 23 Nov 2023 07:38:58 -0700 Date: Thu, 23 Nov 2023 14:38:30 +0000 From: Conor Dooley To: Yu Chien Peter Lin CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Message-ID: <20231123-vigorous-worrier-c8ed0fbbec55@wendy> References: <20231122121235.827122-1-peterlin@andestech.com> <20231122121235.827122-5-peterlin@andestech.com> MIME-Version: 1.0 In-Reply-To: <20231122121235.827122-5-peterlin@andestech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231123_063919_941118_22D4B6AE X-CRM114-Status: GOOD ( 16.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5957413777006613281==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============5957413777006613281== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Myq4yn8cC+6SYdA6" Content-Disposition: inline --Myq4yn8cC+6SYdA6 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 22, 2023 at 08:12:26PM +0800, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string to indicate that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: >=20 > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt >=20 > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. >=20 > Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Cheers, Conor. > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - Add const entry instead of enum (Suggested by Conor) > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..50307554478f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -100,7 +100,11 @@ properties: > const: 1 > =20 > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - const: andestech,cpu-intc > + - const: riscv,cpu-intc > + - const: riscv,cpu-intc > =20 > interrupt-controller: true > =20 > --=20 > 2.34.1 >=20 --Myq4yn8cC+6SYdA6 Content-Type: application/pgp-signature; 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