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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id bi21-20020a056808189500b003b85c5813fdsm919620oib.21.2023.11.27.10.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 10:13:48 -0800 (PST) Received: (nullmailer pid 2053755 invoked by uid 1000); Mon, 27 Nov 2023 18:13:47 -0000 Date: Mon, 27 Nov 2023 12:13:47 -0600 From: Rob Herring To: Georgi Djakov Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, devicetree@vger.kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cgoldswo@quicinc.com, quic_sukadev@quicinc.com, quic_pdaly@quicinc.com, quic_sudaraja@quicinc.com, djakov@kernel.org Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: Add Translation Buffer Unit bindings Message-ID: <20231127181347.GA1953740-robh@kernel.org> References: <20231118042730.2799-1-quic_c_gdjako@quicinc.com> <20231118042730.2799-2-quic_c_gdjako@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231118042730.2799-2-quic_c_gdjako@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_101350_988307_C597D97E X-CRM114-Status: GOOD ( 24.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 17, 2023 at 08:27:25PM -0800, Georgi Djakov wrote: > The "apps_smmu" on the Qualcomm sdm845 platform is an implementation > of the SMMU-500, that consists of a single TCU (Translation Control > Unit) and multiple TBUs (Translation Buffer Units). The TCU is already > being described in the generic SMMU DT schema. Add also bindings for > the TBUs to describe their properties and resources that needs to be > managed in order to operate them. > > In this DT schema, the TBUs are modelled as child devices of the TCU > and each of them is described with it's register space, clocks, power > domains, interconnects etc. > > Signed-off-by: Georgi Djakov > --- > .../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++++++ > .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 89 +++++++++++++++++++ > 2 files changed, 114 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index aa9e1c0895a5..f7f89be5f7a3 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -231,6 +231,18 @@ properties: > enabled for any given device. > $ref: /schemas/types.yaml#/definitions/phandle > > + '#address-cells': > + enum: [ 1, 2 ] > + > + '#size-cells': > + enum: [ 1, 2 ] > + > + ranges: true > + > +patternProperties: > + "^tbu@[0-9a-f]*": > + type: object > + > required: > - compatible > - reg > @@ -453,6 +465,19 @@ allOf: > - description: Voter clock required for HLOS SMMU access > - description: Interface clock required for register access > > + - if: > + properties: > + compatible: > + contains: > + const: qcom,smmu-500 Doesn't match your example. No failure either, so there's some problem with your schema. The issue is the tbu@ entry above has no constraint on child properties. Dropping it would solve the issue. However, having a TBU is not QCom specific, so that doesn't feel right. > + then: > + patternProperties: > + "^tbu@[0-9a-f]*": '+' rather than '*' as 1 is the minimum, not 0. > + $ref: qcom,qsmmuv500-tbu.yaml > + unevaluatedProperties: false > + properties: > + ranges: true > + > # Disallow clocks for all other platforms with specific compatibles > - if: > properties: > diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml > new file mode 100644 > index 000000000000..4dc9d0ca33c9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml > @@ -0,0 +1,89 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm TBU (Translation Buffer Unit) > + > +maintainers: > + - Georgi Djakov > + > +description: > + The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains > + a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides > + debug features to trace and trigger debug transactions. There are multiple TBU > + instances distributes with each client core. > + > +properties: > + $nodename: > + pattern: "^tbu@[0-9a-f]+$" Drop. You defined this in the parent already. > + > + compatible: > + const: qcom,qsmmuv500-tbu > + > + reg: > + items: > + - description: Address and size of the TBU's register space. > + > + reg-names: > + items: > + - const: base Not a useful name. Drop. > + > + clocks: > + maxItems: 1 > + > + interconnects: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + qcom,stream-id-range: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: Stream ID range (address and size) that is assigned by the TBU > + items: > + minItems: 2 > + maxItems: 2 Perhaps implementations other than QCom's needs this? Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel