From: Yicong Yang <yangyicong@huawei.com>
To: <will@kernel.org>, <mark.rutland@arm.com>,
<catalin.marinas@arm.com>, <broonie@kernel.org>,
<james.morse@arm.com>, <anshuman.khandual@arm.com>,
<linux-arm-kernel@lists.infradead.org>
Cc: <jonathan.cameron@huawei.com>,
<shameerali.kolothum.thodi@huawei.com>,
<prime.zeng@hisilicon.com>, <fanghao11@huawei.com>,
<yangyicong@hisilicon.com>, <linuxarm@huawei.com>
Subject: [PATCH v2 2/3] perf: arm_spe: Factor out PMSCR set/clear operations
Date: Thu, 30 Nov 2023 15:46:08 +0800 [thread overview]
Message-ID: <20231130074609.58668-3-yangyicong@huawei.com> (raw)
In-Reply-To: <20231130074609.58668-1-yangyicong@huawei.com>
From: Yicong Yang <yangyicong@hisilicon.com>
Currently we convert the user settings to PMSCR config in
arm_spe_event_to_pmscr() and set/clear the PMSCR register
separately. It blocks further extension for filtering the
exception level. So Factor out PMSCR set/clear operatons
into separate function and only configure the ELx filtering
when setting the register.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/perf/arm_spe_pmu.c | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 05647cfff61d..09570d4d63cd 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -297,7 +297,7 @@ static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
NULL,
};
-/* Convert between user ABI and register values */
+/* Convert between user ABI and register values, except the exception control */
static u64 arm_spe_event_to_pmscr(struct perf_event *event)
{
struct perf_event_attr *attr = &event->attr;
@@ -307,16 +307,32 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event)
reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
+ if (get_spe_event_has_cx(event))
+ reg |= PMSCR_EL1x_CX;
+
+ return reg;
+}
+
+static void arm_spe_pmu_set_pmscr(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ u64 reg = 0;
+
+ reg = arm_spe_event_to_pmscr(event);
if (!attr->exclude_user)
reg |= PMSCR_EL1x_E0SPE;
if (!attr->exclude_kernel)
reg |= PMSCR_EL1x_E1SPE;
- if (get_spe_event_has_cx(event))
- reg |= PMSCR_EL1x_CX;
+ isb();
+ write_sysreg_s(reg, SYS_PMSCR_EL1);
+}
- return reg;
+static void arm_spe_pmu_clr_pmscr(void)
+{
+ write_sysreg_s(0, SYS_PMSCR_EL1);
+ isb();
}
static void arm_spe_event_sanitise_period(struct perf_event *event)
@@ -566,8 +582,7 @@ static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
static void arm_spe_pmu_disable_and_drain_local(void)
{
/* Disable profiling at EL0 and EL1 */
- write_sysreg_s(0, SYS_PMSCR_EL1);
- isb();
+ arm_spe_pmu_clr_pmscr();
/* Drain any buffered data */
psb_csync();
@@ -808,9 +823,7 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags)
write_sysreg_s(reg, SYS_PMSICR_EL1);
}
- reg = arm_spe_event_to_pmscr(event);
- isb();
- write_sysreg_s(reg, SYS_PMSCR_EL1);
+ arm_spe_pmu_set_pmscr(event);
}
static void arm_spe_pmu_stop(struct perf_event *event, int flags)
--
2.24.0
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next prev parent reply other threads:[~2023-11-30 7:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-30 7:46 [PATCH v2 0/3] Enable the profiling of EL0&1 translation regime of ARM SPE Yicong Yang
2023-11-30 7:46 ` [PATCH v2 1/3] arm64/sysreg: Add PMSCR_EL12 and factor out the common fields Yicong Yang
2023-11-30 7:46 ` Yicong Yang [this message]
2023-11-30 7:46 ` [PATCH v2 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime Yicong Yang
2024-04-11 14:28 ` Will Deacon
2024-04-12 9:22 ` Yicong Yang
2024-04-12 9:59 ` Marc Zyngier
2024-04-12 10:12 ` Yicong Yang
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