From: Rob Herring <robh@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: will@kernel.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
suzuki.poulose@arm.com, ilkka@os.amperecomputing.com,
bwicaksono@nvidia.com, YWan@nvidia.com, rwiley@nvidia.com,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Subject: Re: [PATCH 4/5] dt-bindings/perf: Add Arm CoreSight PMU
Date: Fri, 8 Dec 2023 13:33:52 -0600 [thread overview]
Message-ID: <20231208193352.GA1865260-robh@kernel.org> (raw)
In-Reply-To: <bbb4262065cfc906f98165cac074e86dce19599e.1701793996.git.robin.murphy@arm.com>
On Tue, Dec 05, 2023 at 04:51:57PM +0000, Robin Murphy wrote:
> Add a binding for implementations of the Arm CoreSight Performance
> Monitoring Unit Architecture. Not to be confused with CoreSight debug
> and trace, the PMU architecture defines a standard MMIO interface for
> event counters similar to the CPU PMU architecture, where the
> implementation and most of its features are discoverable through ID
> registers.
The implementation is separate from the CPU PMU rather than an MMIO view
of it. Not really clear in my quick read of the spec.
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Conor Dooley <conor+dt@kernel.org>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> .../bindings/perf/arm,coresight-pmu.yaml | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
> new file mode 100644
> index 000000000000..12c7b28eee35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Arm Coresight Performance Monitoring Unit Architecture
> +
> +maintainers:
> + - Robin Murphy <robin.murphy@arm.com>
> +
> +properties:
> + compatible:
> + const: arm,coresight-pmu
> +
> + reg:
> + items:
> + - description: Register page 0
> + - description: Register page 1 (if dual-page extension implemented)
> + minItems: 1
> +
> + interrupts:
> + items:
> + - description: Overflow interrupt
> +
> + cpus:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Don't need a type. Already defined.
> + minItems: 1
1 is always the minimum.
> + description: List of CPUs with which the PMU is associated, if applicable
When is it applicable? Presumably when it is associated with only a
subset of CPUs?
> +
> + arm,64-bit-atomic:
> + type: boolean
> + description: Register accesses are single-copy atomic at doubleword granularity
As this is recommended, shouldn't the property be the inverse.
Maybe the standard 'reg-io-width = <4>' would be sufficient here?
Rob
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next prev parent reply other threads:[~2023-12-08 19:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 16:51 [PATCH 0/5] perf/arm_cspmu: Add devicetree support Robin Murphy
2023-12-05 16:51 ` [PATCH 1/5] perf/arm_cspmu: Simplify initialisation Robin Murphy
2023-12-07 2:16 ` Ilkka Koskinen
2023-12-05 16:51 ` [PATCH 2/5] perf/arm_cspmu: Simplify attribute groups Robin Murphy
2023-12-07 2:47 ` Ilkka Koskinen
2023-12-05 16:51 ` [PATCH 3/5] perf/arm_cspmu: Simplify counter reset Robin Murphy
2023-12-07 2:15 ` Ilkka Koskinen
2023-12-05 16:51 ` [PATCH 4/5] dt-bindings/perf: Add Arm CoreSight PMU Robin Murphy
2023-12-08 19:33 ` Rob Herring [this message]
2023-12-08 21:56 ` Robin Murphy
2023-12-05 16:51 ` [PATCH 5/5] perf/arm_cspmu: Add devicetree support Robin Murphy
2023-12-06 23:43 ` Ilkka Koskinen
2023-12-07 9:43 ` Robin Murphy
2023-12-08 6:35 ` Ilkka Koskinen
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