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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id eu25-20020a0568303d1900b006d99d4ad6d1sm409451otb.59.2023.12.08.11.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 11:33:53 -0800 (PST) Received: (nullmailer pid 2572104 invoked by uid 1000); Fri, 08 Dec 2023 19:33:52 -0000 Date: Fri, 8 Dec 2023 13:33:52 -0600 From: Rob Herring To: Robin Murphy Cc: will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, suzuki.poulose@arm.com, ilkka@os.amperecomputing.com, bwicaksono@nvidia.com, YWan@nvidia.com, rwiley@nvidia.com, Krzysztof Kozlowski , Conor Dooley Subject: Re: [PATCH 4/5] dt-bindings/perf: Add Arm CoreSight PMU Message-ID: <20231208193352.GA1865260-robh@kernel.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231208_113355_625709_BC08E4A3 X-CRM114-Status: GOOD ( 20.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 05, 2023 at 04:51:57PM +0000, Robin Murphy wrote: > Add a binding for implementations of the Arm CoreSight Performance > Monitoring Unit Architecture. Not to be confused with CoreSight debug > and trace, the PMU architecture defines a standard MMIO interface for > event counters similar to the CPU PMU architecture, where the > implementation and most of its features are discoverable through ID > registers. The implementation is separate from the CPU PMU rather than an MMIO view of it. Not really clear in my quick read of the spec. > CC: Rob Herring > CC: Krzysztof Kozlowski > CC: Conor Dooley > Signed-off-by: Robin Murphy > --- > .../bindings/perf/arm,coresight-pmu.yaml | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > new file mode 100644 > index 000000000000..12c7b28eee35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > @@ -0,0 +1,39 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Arm Coresight Performance Monitoring Unit Architecture > + > +maintainers: > + - Robin Murphy > + > +properties: > + compatible: > + const: arm,coresight-pmu > + > + reg: > + items: > + - description: Register page 0 > + - description: Register page 1 (if dual-page extension implemented) > + minItems: 1 > + > + interrupts: > + items: > + - description: Overflow interrupt > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array Don't need a type. Already defined. > + minItems: 1 1 is always the minimum. > + description: List of CPUs with which the PMU is associated, if applicable When is it applicable? Presumably when it is associated with only a subset of CPUs? > + > + arm,64-bit-atomic: > + type: boolean > + description: Register accesses are single-copy atomic at doubleword granularity As this is recommended, shouldn't the property be the inverse. Maybe the standard 'reg-io-width = <4>' would be sufficient here? Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel