From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.linux.dev
Cc: maz@kernel.org, oliver.upton@linux.dev, broonie@kernel.org,
james.morse@arm.com, suzuki.poulose@arm.com,
yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org,
eric.auger@redhat.com, jingzhangos@google.com,
joey.gouly@arm.com, tabba@google.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 10/17] KVM: arm64: Update and fix FGT register masks
Date: Thu, 14 Dec 2023 10:01:50 +0000 [thread overview]
Message-ID: <20231214100158.2305400-11-tabba@google.com> (raw)
In-Reply-To: <20231214100158.2305400-1-tabba@google.com>
New trap bits have been defined since the latest update to this
patch. Moreover, the existing definitions of some of the mask
and the RES0 bits overlap, which could be wrong, confusing, or
both.
Update the bits based on DDI0601 2023-09, and ensure that the
existing bits are consistent.
Subsequent patches will use the generated RES0 fields instead of
specifying them manually. This patch keeps the manual encoding of
the bits to make it easier to review the series.
Fixes: 0fd76865006d ("KVM: arm64: Add nPIR{E0}_EL1 to HFG traps")
Signed-off-by: Fuad Tabba <tabba@google.com>
---
arch/arm64/include/asm/kvm_arm.h | 39 ++++++++++++++++++++------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 7de0a7062625..b0dc3249d5cd 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -344,30 +344,39 @@
* Once we get to a point where the two describe the same thing, we'll
* merge the definitions. One day.
*/
-#define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51))
+#define __HFGRTR_EL2_RES0 BIT(51)
#define __HFGRTR_EL2_MASK GENMASK(49, 0)
-#define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
+#define __HFGRTR_EL2_nMASK (GENMASK(63, 52) | BIT(50))
-#define __HFGWTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51) | \
- BIT(46) | BIT(42) | BIT(40) | BIT(28) | \
- GENMASK(26, 25) | BIT(21) | BIT(18) | \
+#define __HFGWTR_EL2_RES0 (BIT(51) | BIT(46) | BIT(42) | BIT(40) | \
+ BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \
GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
-#define __HFGWTR_EL2_MASK GENMASK(49, 0)
-#define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
+#define __HFGWTR_EL2_MASK (GENMASK(49, 47) | GENMASK(45, 43) | \
+ BIT(41) | GENMASK(39, 29) | BIT(27) | \
+ GENMASK(24, 22) | GENMASK(20, 19) | \
+ GENMASK(17, 16) | GENMASK(13, 11) | \
+ GENMASK(8, 3) | GENMASK(1, 0))
+#define __HFGWTR_EL2_nMASK (GENMASK(63, 52) | BIT(50))
-#define __HFGITR_EL2_RES0 GENMASK(63, 57)
-#define __HFGITR_EL2_MASK GENMASK(54, 0)
-#define __HFGITR_EL2_nMASK GENMASK(56, 55)
+#define __HFGITR_EL2_RES0 (BIT(63) | BIT(61))
+#define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0))
+#define __HFGITR_EL2_nMASK GENMASK(59, 55)
#define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | \
GENMASK(21, 20) | BIT(8))
-#define __HDFGRTR_EL2_MASK ~__HDFGRTR_EL2_nMASK
+#define __HDFGRTR_EL2_MASK (BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
+ GENMASK(41, 40) | GENMASK(37, 22) | \
+ GENMASK(19, 9) | GENMASK(7, 0))
#define __HDFGRTR_EL2_nMASK GENMASK(62, 59)
#define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \
BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \
BIT(22) | BIT(9) | BIT(6))
-#define __HDFGWTR_EL2_MASK ~__HDFGWTR_EL2_nMASK
+#define __HDFGWTR_EL2_MASK (GENMASK(57, 52) | GENMASK(50, 48) | \
+ GENMASK(46, 44) | GENMASK(42, 41) | \
+ GENMASK(37, 35) | GENMASK(33, 31) | \
+ GENMASK(29, 23) | GENMASK(21, 10) | \
+ GENMASK(8, 7) | GENMASK(5, 0))
#define __HDFGWTR_EL2_nMASK GENMASK(62, 60)
#define __HAFGRTR_EL2_RES0 (GENMASK(63, 50) | GENMASK(16, 5))
@@ -375,9 +384,9 @@
#define __HAFGRTR_EL2_nMASK 0UL
/* Similar definitions for HCRX_EL2 */
-#define __HCRX_EL2_RES0 (GENMASK(63, 16) | GENMASK(13, 12))
-#define __HCRX_EL2_MASK (0)
-#define __HCRX_EL2_nMASK (GENMASK(15, 14) | GENMASK(4, 0))
+#define __HCRX_EL2_RES0 (GENMASK(63, 25) | GENMASK(13, 12))
+#define __HCRX_EL2_MASK (BIT(6))
+#define __HCRX_EL2_nMASK (GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
#define HPFAR_MASK (~UL(0xf))
--
2.43.0.472.g3155946c3a-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-12-14 10:03 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 10:01 [PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 01/17] arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1 Fuad Tabba
2023-12-14 10:42 ` Mark Brown
2023-12-14 10:49 ` Mark Brown
2023-12-14 10:01 ` [PATCH v3 02/17] arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1 Fuad Tabba
2023-12-14 10:46 ` Mark Brown
2023-12-14 10:01 ` [PATCH v3 03/17] arm64/sysreg: Add missing system register definitions for FGT Fuad Tabba
2023-12-14 10:50 ` Mark Brown
2023-12-14 10:01 ` [PATCH v3 04/17] arm64/sysreg: Add missing system instruction " Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 05/17] KVM: arm64: Explicitly trap unsupported HFGxTR_EL2 features Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 06/17] KVM: arm64: Add missing HFGxTR_EL2 FGT entries to nested virt Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 07/17] KVM: arm64: Add missing HFGITR_EL2 " Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 08/17] KVM: arm64: Add bit masks for HAFGRTR_EL2 Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 09/17] KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt Fuad Tabba
2023-12-15 13:43 ` Fuad Tabba
2023-12-14 10:01 ` Fuad Tabba [this message]
2023-12-14 10:01 ` [PATCH v3 11/17] KVM: arm64: Add build validation for FGT trap mask values Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 12/17] KVM: arm64: Use generated FGT RES0 bits instead of specifying them Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 13/17] KVM: arm64: Define FGT nMASK bits relative to other fields Fuad Tabba
2023-12-18 9:07 ` Marc Zyngier
2023-12-18 9:16 ` Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits Fuad Tabba
2023-12-15 13:45 ` Fuad Tabba
2023-12-18 9:40 ` Marc Zyngier
2023-12-18 9:56 ` Fuad Tabba
2023-12-18 11:12 ` Marc Zyngier
2023-12-18 11:17 ` Fuad Tabba
2023-12-18 12:25 ` Marc Zyngier
2023-12-18 12:30 ` Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 15/17] KVM: arm64: Fix which features are marked as allowed for protected VMs Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 16/17] KVM: arm64: Mark PAuth as a restricted feature " Fuad Tabba
2023-12-14 10:01 ` [PATCH v3 17/17] KVM: arm64: Trap external trace " Fuad Tabba
2023-12-17 13:41 ` [PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps Will Deacon
2023-12-18 17:11 ` (subset) " Marc Zyngier
2023-12-18 17:15 ` Fuad Tabba
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231214100158.2305400-11-tabba@google.com \
--to=tabba@google.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=eric.auger@redhat.com \
--cc=james.morse@arm.com \
--cc=jingzhangos@google.com \
--cc=joey.gouly@arm.com \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox