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* [PATCH AUTOSEL 6.6 01/18] clk: rockchip: rk3568: Add PLL rate for 292.5MHz
@ 2023-12-18 12:43 Sasha Levin
  2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 02/18] clk: rockchip: rk3128: Fix HCLK_OTG gate register Sasha Levin
  2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 15/18] stmmac: dwmac-loongson: drop useless check for compatible fallback Sasha Levin
  0 siblings, 2 replies; 3+ messages in thread
From: Sasha Levin @ 2023-12-18 12:43 UTC (permalink / raw)
  To: linux-kernel, stable
  Cc: Chris Morgan, Heiko Stuebner, Sasha Levin, mturquette, sboyd,
	linux-clk, linux-arm-kernel, linux-rockchip

From: Chris Morgan <macromorgan@hotmail.com>

[ Upstream commit 1af27671f62ce919f1fb76082ed81f71cb090989 ]

Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel
can run at a requested 60hz (59.96, close enough).

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/rockchip/clk-rk3568.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 16dabe2b9c47f..db713e1526cdc 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -72,6 +72,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
 	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
 	RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
+	RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0),
 	RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH AUTOSEL 6.6 02/18] clk: rockchip: rk3128: Fix HCLK_OTG gate register
  2023-12-18 12:43 [PATCH AUTOSEL 6.6 01/18] clk: rockchip: rk3568: Add PLL rate for 292.5MHz Sasha Levin
@ 2023-12-18 12:43 ` Sasha Levin
  2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 15/18] stmmac: dwmac-loongson: drop useless check for compatible fallback Sasha Levin
  1 sibling, 0 replies; 3+ messages in thread
From: Sasha Levin @ 2023-12-18 12:43 UTC (permalink / raw)
  To: linux-kernel, stable
  Cc: Weihao Li, Heiko Stuebner, Sasha Levin, mturquette, sboyd,
	linux-clk, linux-arm-kernel, linux-rockchip

From: Weihao Li <cn.liweihao@gmail.com>

[ Upstream commit c6c5a5580dcb6631aa6369dabe12ef3ce784d1d2 ]

The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON.

Signed-off-by: Weihao Li <cn.liweihao@gmail.com>
Link: https://lore.kernel.org/r/20231031111816.8777-1-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/rockchip/clk-rk3128.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index aa53797dbfc14..7782785a86e69 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -490,7 +490,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 	GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
 	GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
 	GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
-	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),
+	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
 	GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
 	GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH AUTOSEL 6.6 15/18] stmmac: dwmac-loongson: drop useless check for compatible fallback
  2023-12-18 12:43 [PATCH AUTOSEL 6.6 01/18] clk: rockchip: rk3568: Add PLL rate for 292.5MHz Sasha Levin
  2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 02/18] clk: rockchip: rk3128: Fix HCLK_OTG gate register Sasha Levin
@ 2023-12-18 12:43 ` Sasha Levin
  1 sibling, 0 replies; 3+ messages in thread
From: Sasha Levin @ 2023-12-18 12:43 UTC (permalink / raw)
  To: linux-kernel, stable
  Cc: Krzysztof Kozlowski, Yanteng Si, Conor Dooley, Jiaxun Yang,
	David S . Miller, Sasha Levin, alexandre.torgue, joabreu,
	edumazet, kuba, pabeni, mcoquelin.stm32, netdev, linux-stm32,
	linux-arm-kernel

From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[ Upstream commit 31fea092c6f9f8fb2c40a08137907f5fbeae55dd ]

Device binds to proper PCI ID (LOONGSON, 0x7a03), already listed in DTS,
so checking for some other compatible does not make sense.  It cannot be
bound to unsupported platform.

Drop useless, incorrect (space in between) and undocumented compatible.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 2cd6fce5c9934..b508b68157c77 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -59,11 +59,6 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
 		return -ENODEV;
 	}
 
-	if (!of_device_is_compatible(np, "loongson, pci-gmac")) {
-		pr_info("dwmac_loongson_pci: Incompatible OF node\n");
-		return -ENODEV;
-	}
-
 	plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
 	if (!plat)
 		return -ENOMEM;
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2023-12-18 12:45 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-12-18 12:43 [PATCH AUTOSEL 6.6 01/18] clk: rockchip: rk3568: Add PLL rate for 292.5MHz Sasha Levin
2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 02/18] clk: rockchip: rk3128: Fix HCLK_OTG gate register Sasha Levin
2023-12-18 12:43 ` [PATCH AUTOSEL 6.6 15/18] stmmac: dwmac-loongson: drop useless check for compatible fallback Sasha Levin

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